A variable multi-threshold detection circuit for a sampled baseband signal in the receiver of a communication system using GMSK modulation is disclosed. The circuit comprises an integrate/dump circuit for accumulating a predetermined number of samples of the baseband signal to generate a sum for a present bit, a level selector for selecting a threshold from a plurality of groups of multi-thresholds based on an estimated phase offset and the binary value of two previous bits, a compare circuit for comparing the sum from the integrate/dump circuit with the threshold selected from the level selector to generate a binary value of either one of "0" or "1" for the present bit, and a delay circuit for delaying the present bit to be used by the level selector to determine a next threshold for a next bit.

Variable multi-threshold detection for 0.3-GMSK

An optical receiving apparatus according to the present invention comprises an optical receiver for receiving a signal light input from an optical transmission line, a discriminator for discriminating an output signal of the optical receiver, an evaluator for evaluating transmission characteristics of the optical transmission line according to the received signal of the optical receiver, and a threshold controller for controlling the discrimination threshold of the discriminator according to the evaluated result of the evaluator.

Optical receiving apparatus and method

In controlling a discrimination level V 1 , V 1 is controlled so that discrimination results based on discrimination levels V 1 +ΔV and V 1 -ΔV each become equal to the discrimination result based on the discrimination level V 1 . If the discrimination result based on V 1 +ΔV does not agree with the discrimination result based on V 1 , V 1 is lowered, and if the discrimination result based on V 1 -ΔV does not agree with the discrimination result based on V 1 , V 1 is raised. In controlling a discrimination phase Φ 1 , Φ 1 is controlled so that discrimination results based on discrimination phases Φ 1 +ΔΦ and Φ 1 -ΔΦ each become equal to the discrimination result based on the discrimination phase Φ 1 . If the discrimination result based on Φ 1 +ΔΦ does not agree with the discrimination result based on Φ 1 , Φ 1 is delayed, and if the discrimination result based on Φ 1 -ΔΦ does not agree with the discrimination result based on Φ 1 , Φ 1 is advanced.

Discrimination circuit capable of automatically optimizing discrimination level and discrimination phase

A system and method for the superimposition of differential signals on binary signals. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals

Provided is a test apparatus for testing a device under test, including: a level comparing section that receives a signal under test output from the device under test and outputs a logical value, the logical value indicating a comparison result obtained by comparing a signal level of the signal under test with preset first threshold and second threshold; an acquiring section that acquires the logical value output from the level comparing section, according to a strobe signal supplied thereto; an expected value comparing circuit that determines whether the logical value acquired by the acquiring section corresponds to a preset expected value; and a threshold control section that sets an upper limit and a lower limit of a voltage of the eye mask to the level comparing section as the first threshold and the second threshold, when an eye mask test is performed for determining whether an eye opening of the signal under test is larger than a predefined eye mask.

Test apparatus and test method

A circuit for generating a discrimination voltage level V ref which is used as a reference voltage to discriminate between two adjacent logic levels or an input signal which can have a plurality of different voltage levels generally corresponding to a plurality of respective, different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity (i.e., the voltage range from the level V ref -ΔV to the level V ref +ΔV) of the discrimination voltage level (i.e., the "upper half" thereof being the voltage range from V ref to V ref +ΔV, "ΔV" being a predetermined off-set value) and the frequency at which the levels of the input signals lie in the lower half of the vicinity (i.e., as above defined) of the discrimination level (i.e., the "low half" thereof being the voltage range from V ref -ΔV to V ref ) are compared, and the discrimination level is controlled so that the above two frequencies are the same.

Circuit for generating discrimination voltage level

A circuit for generating a discrimination level voltage which is used as a reference voltage to discriminate between two logic levels adjacent to each other in input signals which generally can be in a state corresponding to one of a plurality of different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity of the discrimination level and the frequency at which the levels of the input signals lie in the lower half of the vicinity of the discrimination level are compared, and the discrimination level is controlled so that the above two frequencies are the same.

Tomoyuki Ohtsuka

Papers

Circuit for generating discrimination voltage level

Circuit for generating discrimination level voltage