We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

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All-digital PLL and transmitter for mobile phones

https://calhoun.nps.edu/bitstream/10945/24839/1/singlesidebandtr00elli.pdf

Single sideband transmission by envelope elimination and restoration.

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

A digitally modulated power amplifier (DPA) in 1.2 V 0.13 mum SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1 % efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications.

A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control

An enhanced data-rates for GSM evolution (EDGE) transmitter using a nonlinear GSM-type PA is presented. It is based on a novel polar loop architecture that employs separate feedback control of the amplitude and the phase of the output signal. With this approach, the problems with AM-to-PM as well as AM-to-AM of the nonlinear PA are essentially eliminated. In addition, this architecture allows for a large dynamic output power control range, as required by the GSM specification. The transmitter uses a standard I/Q interface and does not require the extraction of amplitude and phase modulation in the digital domain. The dual feedback loop ensures robust performance even under voltage-standing wave ratio variations without using an isolator. No external PA filtering is required to meet the transmitter noise in the receive band. The EDGE spectral mask is met with an rms error vector magnitude of <3% at 29 dBm at the antenna, corresponding to 2 dB above nominal maximum output power. There is no mode change between GMSK and EDGE, and the transmitter operates seamlessly in multislot Enhanced General Packet Radio Service. The polar modulation transmitter meets or exceeds the GSM-type approval requirements for both EDGE and GMSK in quad band (850/900/1800/1900 MHz).

Quad-band GSM/GPRS/EDGE polar loop transmitter

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.

A polar modulator transmitter for GSM/EDGE

This paper presents a 65nm 2-TX, 2-RX RF-to-bits basestation transceiver with 200MHz large-signal BW and 450MHz DPD synthesis/observation BW, and LO frequencies from 400MHz to 6GHz. For FDD operation the TRX supports a low-IF mode that meets the dynamic range requirements of GSM basestations. It provides full-band multicarrier (MC) operation in all TDD/FDD 3GPP bands for 2G/3G/4G/5G radios. The SoC includes an 8×16Gb/s SERDES interface, two receivers, two transmitters, and a digital pre-distortion (DPD) feedback RX (FBRX) (Fig. 9.3.1). The FBRX employs a “stitching” system that combines the outputs of both RX basebands to provide 450MHz of observation BW. Three PLLs provide the digital/converter/SERDES clocks, a calibration LO, and an RF LO that meets GSM TX phase-noise requirements. Digital interpolation, decimation, AGC, TX Power control, and calibrations are managed by an integrated ARM Cortex M3. Internal calibration timing is adaptable to support 3G/4G/5G subframe timing requirements. The SoC is a single-chip solution for TDD, and a two-chip set for FDD. GSM requires an external Lo for the RX. Power dissipation in the maximum BW mode (2T/2R/1FBRX, 450/200/450MHz, 0dB RF attenuation, 50% TX/RX duty cycle for TDD) is 4.1W for TDD and 6.6W for FDD.

A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestations

Network densification and FD MIMO in cellular networks require higher levels of base station integration while still meeting stringent performance requirements. We present a monolithic transmitter with integrated digital predistortion and calibration which allows RF agile, multi-carrier operation and enables efficient small cell and FD MIMO systems to be realized below 24dBm/antenna.

A direct-conversion transmitter for small-cell cellular base stations with integrated digital predistortion in 65nm CMOS

A transceiver for 802.11 a/b/g access points supports MRC diversity resulting in a 3dB static sensitivity improvement over a single-receiver implementation. A closed-loop transmit power control scheme achieves 0.5dB accuracy. Receive ADCs and transmit DACs are included, allowing autonomous AGC and transmit power control loops and an all-digital modem/MAC IC. The 25mm2 IC is fabricated in a 0.18mum CMOS process and achieves 3.9dB/4.5dB (low-band/high-band) receive NF and less than -35dB transmit EVM

A Wireless Transceiver with Integrated Data Converters for 802.11a/b/g Access Points

We present a 65nm direct conversion receiver for small cell 3G/4G basestations. The receiver supports up to 100MHz of RF BW and carrier frequencies from 400MHz to 6GHz, with 80dB image rejection and 76dB in-band SFDR. The direct conversion architecture eliminates IF filtering and the need for RF filtering of images and M×N mixing products, reducing basestation size and cost.

Tony Montalvo

Papers

A polar modulator transmitter for GSM/EDGE

A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestations

A direct-conversion transmitter for small-cell cellular base stations with integrated digital predistortion in 65nm CMOS

A Wireless Transceiver with Integrated Data Converters for 802.11a/b/g Access Points

A direct-conversion receiver for multi-carrier 3G/4G small-cell base stations in 65nm CMOS