A flow processing facility, which uses a set of artificial neurons for pattern recognition, such as a self-organizing map, in order to provide security and protection to a computer or computer system supports unified threat management based at least in part on patterns relevant to a variety of types of threats that relate to computer systems, including computer networks. Flow processing for switching, security, and other network applications, including a facility that processes a data flow to address patterns relevant to a variety of conditions are directed at internal network security, virtualization, and web connection security. A flow processing facility for inspecting payloads of network traffic packets detects security threats and intrusions across accessible layers of the IP-stack by applying content matching and behavioral anomaly detection techniques based on regular expression matching and self-organizing maps. Exposing threats and intrusions within packet payload at or near real-time rates enhances network security from both external and internal sources while ensuring security policy is rigorously applied to data and system resources. Intrusion Detection and Protection (IDP) is provided by a flow processing facility that processes a data flow to address patterns relevant to a variety of types of network and data integrity threats that relate to computer systems, including computer networks.

Systems and methods for processing data flows

A mechanism for powering down a functional unit on an integrated circuit having multiple functional units. Some of the functional units are clocked independently of each other. A method and mechanism for indicating to the functional unit whether it is required for use. Also included is a method and mechanism for powering down the functional unit transparent and independent of the rest of the functional units when the functional unit is not required for use.

Method and apparatus for independently stopping and restarting functional units

A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field The microprocessor also includes a latency control register which assures that the functional unit is operational after the functional unit is placed from a low power state to a more fully operational state by changing the corresponding field in the power control register

Microprocessor having software controllable power consumption

A digital circuit configured to receive three or more input signals and produce an output signal corresponding to either an XOR or XNOR of the input signals. In one embodiment of the invention, the circuit includes a first section connected in series with a second section to form a three-input XOR or XNOR gate. The first section is a two-input XOR or XNOR circuit having no more than eight transistors, including two transmission gate pairs. The second section is a two-input XOR or XNOR circuit having no more than six transistors, including one transmission gate pair.

Exclusive or/nor circuit

VLSI implementations of high-performance parallel multipliers are discussed. Circuit building blocks required for partial-product reduction are analyzed and two schemes leading to highly regular layouts are proposed. The circuit implementations related to the first-scheme in three different BiCMOS technologies are discussed. The die size and performance for nominal design rule values are compared, and the trend in scaling the feature sizes is studied. A silicon implementation of a prototype slice of an IEEE double-precision floating point multiplier in a 0.8- mu m double-metal BiCMOS technology is presented. >

Circuit and architecture trade-offs for high-speed multiplication

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The performance characteristics of the ADC and the DAC designed in according with the CCITT recommendations are measured using BIST. Three characteristics have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response. Therefore, test-time is reduced, analog or mixed-signal test equipment is not needed, and finally, test-cost is reduced compared with conventional test methods. This paper describes the BIST design and evaluational results. >

A built-in self-test for ADC and DAC in a single-chip speech CODEC

A microprocessor, including a synchronous type memory having several parts, includes a power saving feature that places at least some parts of the memory in a non-operating state when instructions not requiring access to the memory are executed. An enable signal is generated when access is not required and a signal supplying circuit supplies a synchronous signal when the enable signal is not generated and supplies a signal in a predetermined state to place at least some parts or all parts of the memory in the non-operating state to reduce power consumption.

Microprocessor having built-in synchronous memory with power-saving feature

A semiconductor integrated circuit of master and slave latches and the like that reduces power consumption by supplying a second clock which is a synchronous with a first clock to a slave latch only when the first clock that determines the latch period is supplied to a master latch, discontinuing the supply of the second clock after the master latch completes its latch action in the case that the supply of the first clock to the master latch is discontinued, and discontinuing the supply of clocks when latch action is not required, to reduce loads connected to them.

Semiconductor integrated circuit with master and slave latches

A decimation type digital filter which utilizes the thinned-out signal of a finite impulse response (FIR) filter having N taps for processing the signal by the product sum operation of filter coefficients and the input signals inputted at every first period, in which, on the basis of the ratio K between a first period which is the input signal period and an output signal period and the number of taps N, M (a value obtained by raising below the decimal point of N/K) registers are provided and M successive output signals are processed by the product sum operation in parallel by respective registers, whereby the input signal is not necessarily to be held, a capacity of the register may be minimized and processing may be effected once for each register during the first period or by M number of times of product sum operation in total, thus the operating speed can be reduced to 1/K and the capacity and the operating speed can be optimized.

Decimating digital finite impulse response filter

The operation speed of a full adder is increased by avoiding the necessity of forming the inverse signal for adder operation and deleting the time required for passing through an inverter.

Toru Kengaku

Papers

A built-in self-test for ADC and DAC in a single-chip speech CODEC

Microprocessor having built-in synchronous memory with power-saving feature

Semiconductor integrated circuit with master and slave latches

Decimating digital finite impulse response filter

High speed full adder using complementary input-output signals