A flow processing facility, which uses a set of artificial neurons for pattern recognition, such as a self-organizing map, in order to provide security and protection to a computer or computer system supports unified threat management based at least in part on patterns relevant to a variety of types of threats that relate to computer systems, including computer networks. Flow processing for switching, security, and other network applications, including a facility that processes a data flow to address patterns relevant to a variety of conditions are directed at internal network security, virtualization, and web connection security. A flow processing facility for inspecting payloads of network traffic packets detects security threats and intrusions across accessible layers of the IP-stack by applying content matching and behavioral anomaly detection techniques based on regular expression matching and self-organizing maps. Exposing threats and intrusions within packet payload at or near real-time rates enhances network security from both external and internal sources while ensuring security policy is rigorously applied to data and system resources. Intrusion Detection and Protection (IDP) is provided by a flow processing facility that processes a data flow to address patterns relevant to a variety of types of network and data integrity threats that relate to computer systems, including computer networks.

Systems and methods for processing data flows

Power may be conserved and battery life may be extended in a microprocessor controlled device by providing two microprocessors, one of which is a low power, low performance, low speed processor for performing background tasks, the other of which is a high power, high performance, high speed processor for performing computationally intensive foreground tasks. The low speed processor activates the high speed processor when a high performance task is to be performed. When activating the high performance processor, the low performance processor also controls the device's power supply to provide high voltage to the high speed processor. The high speed processor may run at variable clock speeds, with power consumption of the processor increasing with increasing speed. The high speed processor selects its own clock speed based upon the task to be performed, by including a clock speed in each software subroutine which controls a task. The software subroutine associated with a task is thereby executed at its associated clock speed, which may be chosen to be the lowest possible clock speed consistent with the task to be performed.

Power conservation in microprocessor controlled devices

A mechanism for powering down a functional unit on an integrated circuit having multiple functional units. Some of the functional units are clocked independently of each other. A method and mechanism for indicating to the functional unit whether it is required for use. Also included is a method and mechanism for powering down the functional unit transparent and independent of the rest of the functional units when the functional unit is not required for use.

Method and apparatus for independently stopping and restarting functional units

A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field The microprocessor also includes a latency control register which assures that the functional unit is operational after the functional unit is placed from a low power state to a more fully operational state by changing the corresponding field in the power control register

Microprocessor having software controllable power consumption

Programmability is an important requirement for portable computing and communication devices that must be flexible enough to accommodate a variety of multimedia services and communication capabilities. However, compared to dedicated, application-specific solutions, programmable devices often incur significant performance and power penalties. We present a hybrid architecture template that can be used to implement ultra-low-power programmable processors for signal processing applications.

Ultra-low-power domain-specific multimedia processors

A clock frequency divider for generating a basic clock signal which provides operation timing for a semiconductor integrated circuit operating in accordance with a program. The clock frequency divider comprises a frequency-dividing factor register for storing a frequency-dividing factor which can be rewritten by the program, and a frequency-dividing circuit for frequency-dividing a source clock signal having a fixed frequency in accordance with the frequency-dividing factor stored in the frequency-dividing factor register, whereby a basic clock which provides a processing rate optimum for a program to be executed being obtained.

Programmable clock frequency divider

A microprocessor, including a synchronous type memory having several parts, includes a power saving feature that places at least some parts of the memory in a non-operating state when instructions not requiring access to the memory are executed. An enable signal is generated when access is not required and a signal supplying circuit supplies a synchronous signal when the enable signal is not generated and supplies a signal in a predetermined state to place at least some parts or all parts of the memory in the non-operating state to reduce power consumption.

Microprocessor having built-in synchronous memory with power-saving feature

A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption The PDC half-rate speech codec is implemented in the DSP with 36 mW at 18 V

A 1.8 V 36 mW DSP for the half-rate speech codec

As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole.

Coded incrementer having minimal carry propagation delay

PURPOSE:To cause a switching action to be high-speed and to cause a layout area to be small by composing a buffer of transmission gates, inverters, pull-up and pull-down transistors, etc., without using a NAND gate and a NOR gate. CONSTITUTION:When a 'LOW' is inputted from an enable signal input terminal 12, transmission gates 1 and 2 are made into non-energized states, a 'HIGH' and the 'LOW' are inputted to pull-down and pull-up transistors 3 and 4, respectively, and they are made into conductive states. For such a reason, to P and N type MOS transistors 7 and 8 to pass respective inverters 5 and 6, the 'HIGH' and 'LOW' are inputted, respectively, they are both made into the non-energized states, and an output terminal 18 is made into a high impedance state. On the other hand, when the 'HIGH' is inputted from the enable signal input terminal 12, data D from a data input terminal 11 are outputted in paths of the transmission gate 1 inverter 5 P type MOS transistor 7 and of the transmission gate 2 inverter 6 N type MOS transistor 8, and a delay necessary for it is improved.

Taketora Shiraishi

Papers

Programmable clock frequency divider

Microprocessor having built-in synchronous memory with power-saving feature

A 1.8 V 36 mW DSP for the half-rate speech codec

Coded incrementer having minimal carry propagation delay

Tri-state output buffer