T
Toru Mitsuki
Researcher at Panasonic
Publications - 17
Citations - 319
Toru Mitsuki is an academic researcher from Panasonic. The author has contributed to research in topics: Semiconductor & Semiconductor device. The author has an hindex of 8, co-authored 17 publications receiving 319 citations.
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Patent
Semiconductor device and fabrication method therefor
Shunpei Yamazaki,Toru Mitsuki,Kenji Kasahara,Taketomi Asami,Tamae Takano,Takeshi Shichi,Chiho Kokubo +6 more
TL;DR: In this article, a semiconductor material which contains silicon as its main component and 0.1-10 atomic % of germanium is used as a first layer, and an amorphous silicon film as a second layer.
Patent
Semiconductor device and method for manufacturing same
TL;DR: In this paper, a semiconductor device having plural active and passive elements on one semiconductor substrate is manufactured in the following cost effective manner, even when the active or passive elements include double sided electrode elements.
Patent
Thin film transistors and semiconductor device
Shunpei Yamazaki,Toru Mitsuki,Kenji Kasahara,Taketomi Asami,Tamae Takano,Takeshi Shichi,Chiho Kokubo,Yasuyuki Arai +7 more
TL;DR: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor films containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto.
Patent
Method of manufacturing a semiconductor device having a crystallized semiconductor film
TL;DR: In this paper, a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed.
Patent
Semiconductor device with rod like crystals and a recessed insulation layer
TL;DR: In this article, an under-insulating layer is formed on a quartz or semiconductor substrate by flattening the surface of an insulating film to form the under insulating layer, and the surface roughness of the surface is made 0.3 nm or less.