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Showing papers by "Toshihiko Kosugi published in 1998"


Journal ArticleDOI
TL;DR: In this paper, a 120-kilo-gate fully functional gate-array LSI consisting of basic cells with a single-contact layout (single-contact cells) is fabricated on 300-KG sea-of-gate (SOG) type gate arrays using 0.25-µm FD complementary metal-oxide-semiconductor separation by implanted oxygen (CMOS/SIMOX) technology with selective W chemical vapor deposition (CVD).
Abstract: A 120-kilo-gate (KG) fully functional gate-array LSI consisting of basic cells with a single-contact layout (single-contact cells) is fabricated on 300-KG sea-of-gate (SOG) type gate arrays using 0.25-µm ultra-thin-film fully-depleted (FD) complementary metal-oxide-semiconductor separation by implanted oxygen (CMOS/SIMOX) technology with selective W chemical vapor deposition (CVD). This paper shows that the performance of circuits made with single-contact cells can be as high as that with multi-contact cells, when the source/drain sheet resistance is below 5 Ω/sq. It also shows that selective W-CVD with the hydrogenation-and-hydrogen-termination (HHT) treatment can provide this sheet resistance even in ultra-thin-film silicon-on-insulator (SOI) substrates with a 50-nm-thick silicon layer. Single-contact cells built with selective W-CVD were applied to metal-oxide-semiconductor field effect transistors (MOSFETs), 2-input NAND circuits, and gate-array LSIs. Consequently, these cells did not degrade the drain current of transistors, or raise the gate delay time of the circuits. Single-contact cells built with W did not lower the yield of LSIs up to 120 KG compared to LSIs made with multi-contact cells without W. Furthermore, the 120-KG LSI consisting of single contact cells with W had no decrease in speed, compared to one with multi-contact cells. These results indicate that the selective W-CVD is a promising technology to increase the packing density of LSIs made with ultra-thin-film FD CMOS/SOI.

3 citations


Journal ArticleDOI
TL;DR: In this paper, selective tungsten (W) chemical-vapor-deposition (CVD) with hydrogenation and hydrogen-termination (HHT) is applied to ultra-thin-film fully-depleted (FD) metaloxide-semiconductor field effect transistors (MOSFETs) on SIMOX (Separation by IMplanted OXygen) for reducing the sheet resistance of source and drain regions.
Abstract: Selective tungsten (W) chemical-vapor-deposition (CVD) with hydrogenation and hydrogen-termination (HHT) is applied to ultra-thin-film fully-depleted (FD) metal-oxide-semiconductor field effect transistors (MOSFETs) on SIMOX (Separation by IMplanted OXygen) for reducing the sheet resistance of source and drain regions. 0.25-µm-gate MOSFETs on SIMOX (MOSFETs/SIMOX) with a top Si layer with a thickness of 50 nm are fabricated using selective W-CVD, and their characteristics, including hot-carrier effects and latch-onset voltage, are systematically investigated. It is found that selective W-CVD with HHT can reduce the source/drain (S/D) sheet resistance in 50-nm-thick ultra-thin-film SIMOX to 10 Ω/sq. or less. This ensures that W deposition increases the drain saturation current. It is also found that W deposition largely suppresses the parasitic bipolar effects. Consequently, the anomalous subthreshold slope diminishes, hot carrier reliability improves, and the latch-onset voltage rises to over 2.5 V. Moreover, it is clarified that the parasitic bipolar effects are largely suppressed when the W layer is within 0.3 µm from the source/body junction. This is because W effectively extracts the holes generated by impact ionization, and thus suppresses the accumulation of holes which would otherwise induce an increase in the body potential.

2 citations


Proceedings ArticleDOI
04 Sep 1998
TL;DR: In this article, selective W-CVD with hydrogenation and termination treatment was developed to reduce source/drain sheet resistance in ultra-thin-film fully-depleted CMOSFET's/SIMOX, and it was applied to 0.25-micrometer-gate gate-array LSIs.
Abstract: Selective W-CVD technology with hydrogenation and hydrogen- termination treatment was developed to reduce source/drain sheet resistance in ultra-thin-film fully-depleted CMOSFET's/SIMOX, and it was applied to 0.25-micrometer-gate gate-array LSIs. It is clarified that this technology ensures single-contact cells, which are vital for higher packing density, with no degradation of device characteristics, circuit performance, and LSI yield. Moreover, recent results for devices with a W-covered gate/source/drain are presented.

1 citations