The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

A circuit is disclosed which converts CMOS logic input signals to ECL output signals. A pair of FETs, arranged as a conventional CMOS inverter, responds to the CMOS logic input signals and drives a bipolar transistor operating as a voltage follower. The emitter of the bipolar transistor serves as the output of the buffer providing the ECL output signals. A resistor having a predetermined resistance couples between a voltage source and the base of the bipolar transistor. First one of the pair of FETs couples a constant current source to the resistor and the base of the bipolar transistor when the buffer is supplying an ECL logical "zero" logic signal. The current from the current source passing through the resistor establishes the ECL logical "zero" output voltage. Second one of the pair of FETs shunts the resistor when the buffer is supplying an ECL logical "one" output, allowing faster transitioning of the output of the buffer from an ECL logical "zero" to a logical "one". Further, the current from the current source compensates for variations in the resistance of the resistor to assure a substantially constant difference between the ECL logical "one" and the ECL logical "zero" output voltages with variations in the resistance of the resistor from the manufacture thereof.

CMOS to ECL output buffer

A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal The slave portion of the flip-flop includes a second bistable cell that is coupled to the first cell and a second control circuit for changing the state of the second cell in response to the output of the first cell and to a clock signal The flip-flop is intended to be implemented using CMOS technology, and is capable of performing at frequencies greater than a gigahertz with low power consumption The circuit configuration is highly symmetric, so that the master and slave portions may be interchanged

High-speed low-power flip-flop

A driver for providing binary signals from a data system to a transmission line is disclosed. The driver includes a first field-effect transistor (FET) coupled between an output node and ground for conducting current from the output node to ground. The output node is connectable to the transmission line. An initial charging stage provides an initial charging current to the gate of the first FET for a period of time not to exceed an initial charging time period. The initial charging time period has a length approximately equal to a period of time necessary to increase the gate voltage of the first FET from ground to the threshold voltage of the first FET. A main charging stage provides a main charging current to the gate of the first FET for a period of time not to exceed a main charging time period. A discharging stage provides a discharging current from the gate of the first FET to ground. Finally, a temperature compensation circuit is coupled to the initial charging stage, the main charging stage, and the discharging stage for adjusting the level of the initial charging current, the main charging current, and the discharging current to compensate for variations in temperature and for controlling the length of the main charging time period.

Programmable slew rate CMOS buffer and transmission line driver with temperature compensation

A driver for providing binary signals from a data system to a transmission line is disclosed. A first n-channel transistor has its drain coupled to the transmission line and its source coupled to ground. The channel of the first n-channel transistor has a width that is greater than its length. A first inverter stage conducts current from a first voltage supply to the gate of the first n-channel transistor in order to switch the first n-channel transistor into a conductive state and conducts current from the gate of the first n-channel transistor to ground in order to switch the first n-channel transistor into a non-conductive state. A discharge circuit provides a discharge path from the gate of the first n-channel transistor to ground during a discharge time period and then removes the discharge path at the end of the discharge time period. A temperature compensation circuit may be coupled to the first inverter stage to adjust the level of current conducted to the gate of the first n-channel transistor and the level of current conducted from the gate of the first n-channel transistor to compensate for variations in temperature.

CMOS bus and transmission line driver having compensated edge rate control

A temperature compensated differential level shift circuit (Fig. 2). An ECL type buffered differential circuit employs a source of threshold voltage, VT (Fig. 3), which matches the temperature-dependent characteristic of the input section of the level shift circuit. In a preferred embodiment, s Schottky diode (52) is provided in the output section of a bandgap reference voltage generator (Fig. 3) which matches the temperature dependence of a Schottky diode (30) in the input section of the level shift circuit (Fig. 2). As temperature shifts, the threshold voltage will shift in a manner that tracks the temperature-produced shift in the input voltage as it passes through the Schottky diode in the input section of the level shift circuit. Matched PNP or NPN transistors (70, 72 and 71, 73 ) may also be used in the input section of the level shift circuit (Figs. 6A, 7A) and in the output section of the bandgap reference voltage generator (Figs. 6B, 7B).

Temperature compensated ttl to ecl translator

Disclosed is a digital signal translation circuit for translating a first type signal to a second type signal which comprises a master latch and a slave latch. The master latch latches the incoming first type signal during a first portion of the clock signal. A slave latch latches the master latch output and generates a differential output. The differential output of the slave drives an output driver circuit which generates the second type signal.

Tsen-Shau Yang

Papers

Temperature compensated ttl to ecl translator

Digital signal level translation/master-slave flip flop with look-ahead

Digital signal translation circuit