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Showing papers by "Ulrich Rückert published in 1994"


Proceedings Article
01 Jan 1994
TL;DR: In this article, a fabricated integrated circuit for self-organizing feature maps is presented, which is based on the idea that restrictions to the algorithm can simplify the implementation, using the Manhattan distance and a special treatment of the adaptation factor α decreases the necessary chip area.
Abstract: The use of self-organizing feature maps in real-time applications requires a high computational performance. Especially for embedded systems neural network chips are needed. In this paper a fabricated integrated circuit for self-organizing feature maps is presented. The architecture of this digital chip is based on the idea, that restrictions to the algorithm can simplify the implementation. Using the Manhattan Distance and a special treatment of the adaptation factor α decreases the necessary chip area, so that a high number of processor elements can be integrated on one chip. The effects of these restrictions on the function of the self-organizing feature map are discussed. The paper concludes with performance figures for a system architecture based on these chips

17 citations


01 Jan 1994
TL;DR: In recent years there has been an increasing interest in the use of artificial neural networks for technical applications, particularly attractive is the application of ANNs in those domains where at present humans outperform any currently available high performance computers, e.g. in areas like auditory perception, vision, or sensory-motor control.
Abstract: In recent years there has been an increasing interest in the use of artificial neural networks (ANNs) for technical applications (e.g. Rogers 1990). Particularly attractive is the application of ANNs in those domains where at present humans outperform any currently available high performance computers, e.g. in areas like auditory perception, vision, or sensory-motor control. Neural information processing is expected to have a wide applicability in areas that require a high degree of flexibility and the ability to operate in uncertain environments where information usually is partial, fuzzy, or even contradictory. The computing power of biological neural networks stems to a large extend from a highly parallel, fine-grained and distributed processing and storage of information as well as from the capability of learning.

4 citations


Proceedings ArticleDOI
05 Sep 1994
TL;DR: An example of a hybrid system architecture integrating connectionist models and symbolic knowledge processing is introduced and the inclusion of non-symbolic knowledge sources, transformation of learned knowledge into a symbolic form and associative storage as well as retrieval of information are discussed.
Abstract: An example of a hybrid system architecture integrating connectionist models and symbolic knowledge processing is introduced. In particular the inclusion of non-symbolic knowledge sources (data from physical processes, measurements, sensors etc.), transformation of learned knowledge into a symbolic form (rule extraction) and associative storage as well as retrieval of information are discussed by means of application examples. Finally, parallel hardware support for the proposed hybrid system architecture is presented.

3 citations



01 Jan 1994
TL;DR: The use of general purpose microprocessors has further advantages, e.g. they are relative cheap compared to ASICs of low or medium quantity, they are currently available, and they utilize the highest integration level of state of the art VLSI technologies as mentioned in this paper.
Abstract: The implementation of neural networks by means of multiprocessor architectures is a promising compromise between flexible modelling — the system is still program controlled -and a complete implementation by means of special-purpose VLSI chips. The use of general purpose microprocessors has further advantages, e.g. they are relative cheap compared to ASICs of low or medium quantity, they are currently available, and they utilize the highest integration level of state of the art VLSI technologies.