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Showing papers by "Ulrich Rückert published in 2000"


Proceedings ArticleDOI
06 Sep 2000
TL;DR: A special software for configuring, monitoring and testing the switch hardware was developed and experiments for the evaluation of the Ethernet Medium Access Control Pause operation in automation systems are described.
Abstract: Ethernet networks for automation systems promise standardized interworking between completely different devices from field level up to office level without connection and conversion difficulties. As Ethernet was not originally developed considering automation system requirements, its qualification, especially regarding topology and determinism demands, has to be examined. Theoretical calculations on topology influence are completed by measurements on switch hardware. A special software for configuring, monitoring and testing the switch hardware was developed. Further experiments for the evaluation of the Ethernet Medium Access Control Pause operation in automation systems are also described.

35 citations


Proceedings ArticleDOI
13 Sep 2000
TL;DR: In this paper, the authors address the problem of estimating the power and area consumption of on-chip interconnects for standard cell ASIC processes and introduce a set of analytic investigations on buses, crossbar switches, and multiplexors.
Abstract: This paper addresses the problem of estimating the power and area consumption of on-chip interconnects for standard cell ASIC processes. We introduce a set of analytic investigations on buses, crossbar switches, and multiplexors. Furthermore, we prove the accuracy of the results by comparing them with gate-level power-estimations on a double metal 0.6 /spl mu/m CMOS technology.

27 citations




Proceedings ArticleDOI
06 Sep 2000
TL;DR: The authors present the development of a distributed software simulator especially designed for large automation systems consisting of thousands of microcontroller based devices.
Abstract: In modern building automation systems an increasing number of devices with computational facilities exchange data and interoperate using underlying control networks. Discontinuous and nonlinear processes, synchronization effects and delays in communication lead to systems with highly complex behavior. Analytical methods often do not meet the demands for the evaluation of such systems. As an alternative approach, discrete event simulation gains more and more importance. The authors present the development of a distributed software simulator especially designed for large automation systems consisting of thousands of microcontroller based devices. An existing and expanding building automation system used to validate the simulator and which forms a base for modeling a large system is also described.

7 citations


Proceedings ArticleDOI
03 Sep 2000
TL;DR: This paper focuses on how simple behaviours can be learnt autonomously using a bootstrapping method and the neural implementation developed is transferable to other artificial autonomous agents with different sensors and effector suites.
Abstract: To understand the behaviour of natural autonomous systems, research is carried out on artificial autonomous agents. The paper focuses on how simple behaviours can be learnt autonomously using a bootstrapping method. Firstly, a two dimensional self-organising map is realised which provides the agent's sense of orientation. Once this relative positioning system has been established, the agent learns to navigate towards a target using the reinforcement learning technique of Q-learning. Since only neural network processing is used, this technique emulates the distributed and adaptive information processing found in natural autonomous systems. Furthermore, due to its generality, the neural implementation developed is transferable to other artificial autonomous agents with different sensors and effector suites.

4 citations


Book ChapterDOI
27 Aug 2000
TL;DR: This paper introduces a new FPGA based prototyping environment, on which a full functional embedded system can be implemented, and presents the application of this environment to the development of a network processor which consists of a processor core and an Ethernet controller.
Abstract: The rapid advances in microelectronic circuit design have dramatically increased the design complexity of modern integrated devices. One approach to fit the time-to-market requirements is the use of rapid prototyping environments. In this paper we introduce a new FPGA based prototyping environment, on which a full functional embedded system can be implemented. The main distinction to other environments is the incorporation of a synthesizable and configurable microprocessor core into the design space. Furthermore we present the application of this environment to the development of a network processor which consists of a processor core and an Ethernet controller.

3 citations


01 Jan 2000
TL;DR: The Verschaltung von Festplatten zu Feldern zur effizienten Verwaltung of riesigen Datenmengen gewinnt immer======¯¯¯¯¯¯mehr an Bedeutung as mentioned in this paper.
Abstract: Die Verschaltung von Festplatten zu Feldern zur effizienten Verwaltung von riesigen Datenmengen gewinnt immer mehr an Bedeutung. Durch den Einsatz aktiver Einheiten zum Aufbau von internen Verbindungsstrukturen zwischen den Festplatten ist es moglich, an das System angeschlossene Dateiserver von vielen Basisaufgaben zu entlasten. Diese aktiven Router basieren neben einer Routingeinheit und den Schnittstellen zu den Festplatten und den Dateiservern auf einem Mikroprozessor und einer rekonfigurierbaren Einheit. Im Rahmen dieser Arbeit werden mogliche Einsatzgebiete von aktiven Routern, Untersuchungen zu deren Dimensionierung und praktischen Implementierungen der Hardware vorgestellt.

2 citations


01 Jan 2000
TL;DR: In this article, analytische untersuchungen bezuglich der Verbindungsstrukturen Bus, Crossbar-Switch and Multiplexer vorgestellt and mit============Ergebnissen einer Simulation fur eine 0,6 μm CMOS Technologie verglichen.
Abstract: Diese Arbeit befast sich mit der Aufgabe, den Energie- und Flachenverbrauch von Verbindungsstrukturen auf einem Chip fur Standardzellen-Prozesse auf einer hohen Abstraktionsebene abzuschatzen. Es werden analytische Untersuchungen bezuglich der Verbindungsstrukturen Bus, Crossbar-Switch und Multiplexer vorgestellt und mit den Ergebnissen einer Simulation fur eine 0,6 μm CMOS Technologie verglichen. Bezuglich der Abschatzung des Energieverbrauchs ergab sich ein mittlerer Fehler von etwa 10%.