Showing papers by "Uwe Meyer-Baese published in 2006"
17 Apr 2006
TL;DR: Critical however with this design flow are: quality-of-results, sophistication of Simulink block library, compile time, cost and availability of development boards, and cost, functionality, and ease of use of the FPGA vendor provided design tools.
Abstract: Design of current DSP applications using state-of-the art multi-million gates devices requires a broad foundation of the
engineering shlls ranging from knowledge of hardware-efficient DSP algorithms to CAD design tools. The requirement of short time-to-market, however, requires to replace the traditional HDL based designs by a MatLab/Simulink based design flow. This not only allows the over 1 million MatLab users to design FPGAs but also to by-pass the hardware design engineer leading to a significant reduction in development time. Critical however with this design flow are: (1) quality-of-results, (2) sophistication of Simulink block library, (3)
compile time, (4) cost and availability of development boards, and (5) cost, functionality, and ease-of-use of the FPGA
vendor provided design tools.
28 citations
01 Dec 2006
TL;DR: It will be shown that pipelined RAG-n designs achieve on average a gain of 71% in area, equivalent performance in speed, and a 56% improvement in cost compared with DA-based designs.
Abstract: The paper starts with an overview of distributed arithmetic (DA) and n-dimensional reduced adder graph (RAG-n) multiplierless filter design methods. Since DA designs are table-based and RAG-n designs are adder-based, FPGA synthesis design data are used for a realistic comparison. Benchmark FIR filters (Goodman and Carey, 1977) of length 11 to 63 are compiled. For a wide set of realistic design examples, it will be shown that pipelined RAG-n designs achieve on average a gain of 71% in area, equivalent performance in speed, and a 56% improvement in cost compared with DA-based designs
23 citations
01 Aug 2006
TL;DR: The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient.
Abstract: This paper presents a technique for intellectual property protection (IPP) of systems to be implemented over programmable devices. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction requiring minimal modifications to the system. So it is possible to detect the ownership rights without interfering the normal operation of the system. The IPP technique has been implemented on FPL devices, not disrupting the functionality neither significantly degrading the performance.
17 citations
11 Sep 2006
TL;DR: This technique relies on embedding a digital signature in non used cells of look-up tables of RNS-based designs at HDL design level, which enables the protection of author rights in the development and distribution of these designs as reusable modules (IP cores) in an efficient and transparent way.
Abstract: This paper presents a watermarking technique for Intellectual Property Protection (IPP) of circuits based on the residue number system (RNS). This technique relies on embedding a digital signature in non used cells of look-up tables of RNS-based designs at HDL design level; this enables the protection of author rights in the development and distribution of these designs as reusable modules (IP cores) in an efficient and transparent way. The embedded signature uniquely identifies both the design origin and the recipient, while being difficult to detect and/or remove, its extraction requires minimal modifications to the system. The presented IPP scheme has been implemented on a variety of FPL devices, not disrupting the functionality neither significantly degrading the performance of the example systems.
2 citations
17 Apr 2006
TL;DR: The turbo principle applied to LMS ADF is analogous to the turbo principle used for error correction decoders: first, an "interleaver" is used to minimize crosscorrelation, secondly, an iterative improvement which uses the same data set several times is implemented using the standard LMS algorithm.
Abstract: Adaptive digital filters (ADFs) are, in general, the most sophisticated and resource intensive components of modern digital signal processing (DSP) and communication systems. Improvements in performance or the complexity of ADFs can have a significant impact on the overall size, speed, and power properties of a complete system. The least mean square (LMS) algorithm is a popular algorithm for coefficient adaptation in ADF because it is robust, easy to implement, and a close approximation to the optimal Wiener-Hopf least mean square solution. The main weakness of the LMS algorithm is the slow convergence, especially for non Markov-1 colored noise input signals with high eigenvalue ratios (EVRs). Since its introduction in 1993, the turbo (supercharge) principle has been successfully applied in error correction decoding and has become very popular because it reaches the theoretical limits of communication capacity predicted 5 decades ago by Shannon. The turbo principle applied to LMS ADF is analogous to the turbo principle used for error correction decoders: First, an "interleaver" is used to minimize crosscorrelation, secondly, an iterative improvement which uses the same data set several times is implemented using the standard LMS algorithm. Results for 6 different interleaver schemes for EVR in the range 1-100 are presented.