The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.

https://www.eecs.ucf.edu/~jinyier/courses/EEE4932/Papers_Final/HARPOON%20-%20An%20Obfuscation-Based%20SoC%20Design%20Methodology%20for%20Hardware%20Protection.pdf

HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources.

/pdf/a-survey-and-evaluation-of-fpga-high-level-synthesis-tools-4pv9ke4ji3.pdf

A Survey and Evaluation of FPGA High-Level Synthesis Tools

In this paper, we suggest a variational model for optic flow computation based on non-linearised and higher order constancy assumptions. Besides the common grey value constancy assumption, also gradient constancy, as well as the constancy of the Hessian and the Laplacian are proposed. Since the model strictly refrains from a linearisation of these assumptions, it is also capable to deal with large displacements. For the minimisation of the rather complex energy functional, we present an efficient numerical scheme employing two nested fixed point iterations. Following a coarse-to-fine strategy it turns out that there is a theoretical foundation of so-called warping techniques hitherto justified only on an experimental basis. Since our algorithm consists of the integration of various concepts, ranging from different constancy assumptions to numerical implementation issues, a detailed account of the effect of each of these concepts is included in the experimental section. The superior performance of the proposed method shows up by significantly smaller estimation errors when compared to previous techniques. Further experiments also confirm excellent robustness under noise and insensitivity to parameter variations.

Highly accurate optic flow computation with theoretically justified warping

As the electronic component supply chain grows more complex due to globalization, with parts coming from a diverse set of suppliers, counterfeit electronics have become a major challenge that calls for immediate solutions. Currently, there are a few standards and programs available that address the testing for such counterfeit parts. However, not enough research has yet addressed the detection and avoidance of all counterfeit partsVrecycled, remarked, overproduced, cloned, out-of-spec/defective, and forged documentationVcurrently infiltrating the electronic component supply chain. Even if they work initially, all these parts may have reduced lifetime and pose reliability risks. In this tutorial, we will provide a review of some of the existing counterfeit detection and avoidance methods. We will also discuss the challenges ahead for im- plementing these methods, as well as the development of new detection and avoidance mechanisms.

/pdf/counterfeit-integrated-circuits-a-rising-threat-in-the-1cfbkrfgxn.pdf

Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain

In this paper we describe a new nonlinear principal component analyzer and apply it in connection with a new compression scheme to lossy compression of digitized mammograms. We use a 'neural-gas' network for codebook design and several linear and nonlinear principal component method as a preprocessing technique. First, we analyze mathematically the nonlinear, single-layer neural network and show that the equilibrium points of this system are global asymptotically stale. Both a regular Hebbian rule and an anti-Hebbian rule are used for the adaptation of the connection weights between the constituent units. The, we investigate the performance of the compression scheme depending on the blocksize, codebook and number of chosen principal components. The nonlinear principal component method shows the best compression reslut in combination with the 'neural-gas' network.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Neural nonlinear principal component analyzer for lossy compressed digital mammography

This chapter gives an overview of the part of the very high-speed integrated circuit hardware description language (VHDL) used in the book. As with most languages, we start with lexical preliminary and then discuss data types, operations, and statements of the VHDL language. Coding tips, additional help, and further reading complete the chapter. If your preferred HDL is Verilog, you may skip this chapter and continue with Chap. 4.

Microprocessor Component Design in VHDL

Conventional vector-based simulators for quantum computers are quite limited in the size of the quantum circuits they can handle, due to the worst-case exponential growth of even sparse representations of the full quantum state vector as a function of the number of quantum operations applied. However, this exponential-space requirement can be avoided by using general space-time tradeoffs long known to complexity theorists, which can be appropriately optimized for this particular problem in a way that also illustrates some interesting reformulations of quantum mechanics. In this paper, we describe the design and empirical space-time complexity measurements of a working software prototype of a quantum computer simulator that avoids excessive space requirements. Due to its space-efficiency, this design is well-suited to embedding in single-chip environments, permitting especially fast execution that avoids access latencies to main memory. We plan to prototype our design on a standard FPGA development board.

A space-efficient quantum computer simulator suitable for high-speed FPGA implementation

Fast implementation of convolution and discrete Fourier transform (DFT) computations are frequent problems insignal and image processing. These operations typically use fast Fourier transform (FFT) algorithms. NumberTheoretic Transforms (NTTs) over a finite group of primes can also used for this purpose. Using the NTT overFermat primes (2 + 1) in field programmable gate array (FPGA) designs is advantageous, because the arithmetic

High-Performance Implementation of Convolution on Multiple Field-Programmable Gate Array Boards Using Number Theoretic Transforms Defined Over the Eisenstein Residue Number System

This chapter gives an overview of the part of the Verilog hardware description language used in later chapters. As with most languages, we start with lexical preliminary and then discuss data types, operations, and statements of the Verilog language. Coding tips, additional help, and further reading complete the chapter. If your preferred HDL is VHDL, you may skip this chapter at first reading.

Uwe Meyer-Baese

Papers

Neural nonlinear principal component analyzer for lossy compressed digital mammography

Microprocessor Component Design in VHDL

A space-efficient quantum computer simulator suitable for high-speed FPGA implementation

High-Performance Implementation of Convolution on Multiple Field-Programmable Gate Array Boards Using Number Theoretic Transforms Defined Over the Eisenstein Residue Number System

Microprocessor Component Design in Verilog