This paper presents the use of B-splines as a tool in various digital signal processing applications. The theory of B-splines is briefly reviewed, followed by discussions on B-spline interpolation and B-spline filtering. Computer implementation using both an efficient software viewpoint and a hardware method are discussed. Finally, experimental results are presented for illustrative purposes in two-dimensional image format. Applications to image and signal processing include interpolation, smoothing, filtering, enlargement, and reduction.

Cubic splines for image interpolation and digital filtering

The history and fundamentals of distributed arithmetic (DA) are presented. Ways to increase the speed of DA multiplication are described. DA is applied to a biquadratic digital filter, providing an example of vector dot-product and vector-matrix-product mechanization. Applications to transformers and nonlinear and/or nonstationary processing with DA are discussed. It is seen that DA is a very efficient means to mechanize computations that are dominated by inner products. >

Applications of distributed arithmetic to digital signal processing: a tutorial review

A new approach to the implementation problem of digital filters is presented. This approach capitalizes on recent advances in semiconductor memory technology and is shown to offer significant reductions in cost and power consumption for the same speed of operation as that of existing realizations. Furthermore, this approach makes possible speeds of operation which cannot be achieved by existing realizations. The proposed approach yields a very flexible hardware configuration and a discussion of the various options is presented together with a comparison to existing realizations. The mean-squared error resulting from the use of finite word length is analyzed.

A new hardware realization of digital filters

In this paper, we present the design optimization of one- and two-dimensional fully pipelined computing structures for area-delay-power-efficient implementation of finite-impulse-response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the lookup tables (LUT) for DA-based computation to decide on suitable area time tradeoff. It is observed that by using smaller address lengths for DA-based computing units, it is possible to reduce the memory size, but on the other hand that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density, and energy throughput are estimated for different filter orders and address lengths. Analysis of the results obtained indicate that performance metrics of the proposed implementation is broadly in line with theoretical expectations. It is found that the choice of address length yields the best of area-delay-power-efficient realizations of the FIR filter for various filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.

FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

A classification is given of the various possible nonlinear effects that can occur in recursive digital filters due to signal quantization and adder overflow. The effects include limit cycles, overflow oscillations, and quantization noise. A review is given of recent literature on this subject. Alternative methods of avoiding some of these nonlinear phenomena are discussed.

Effects of quantization and overflow in recursive digital filters

A digital filter either of a recursive or transversal type responsive to successive digitally encoded analog signal samples of m bits each. The filter comprises an accumulator for multiplying and summing a weighted hybrid value obtained from a memory medium addressed by a selected one of the m bits of each of N digitally encoded signal samples. If the bits of the N samples used for addressing the memory are derived from successive input signals only, then the filter is of the transversal type. If V of the N signals whose bits are used for addressing are from the input samples and R of the N signals whose bits also are used for addressing are obtained from filter output signals, then the filter is recursive. By addressing the memory with the binary value of like bit positions of the signal samples, then a hybrid value may be stored, which hybrid value need only be multiplied and combined by the accumulator. This permits the use of a substantially smaller memory than that required if the digits of the signals looked up the completed weighted function.

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Papers

Digital filter for pcm encoded signals