DRAM cell arrays having a cell area of about 4F 2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

DRAM layout with vertical FETs and method of formation

Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a second contact layer vertically separated by an oxide layer. A single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical body region which separates an ultra thin single crystalline vertical first source/drain region and an ultra thin single crystalline vertical second source/drain region. A floating gate opposes the ultra thin single crystalline vertical body region, and a control gate separated from the floating gate by an insulator layer.

Flash memory with ultra thin vertical body transistors

Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

Peripheral gate stacks and recessed array gates

A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. The decoder further includes a number of single crystalline ultra thin vertical transistor that are selectively disposed adjacent the number of vertical pillars. Each single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A plurality of buried source lines formed of single crystalline semiconductor material are disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array. And, each of the number of address lines is disposed in a trench between rows of the pillars for addressing the ultra thin single crystalline vertical body regions of the single crystalline vertical transistors that are adjacent to the trench.

Memory address and decode circuits with ultra thin body transistors

Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. In each memory cell a single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions, and a gate opposing the vertical body region and separated therefrom by a gate oxide. A plurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Also, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.

Open bit line DRAM with ultra-thin body transistors

The continuous scaling of MOSFET technology into the deep sub-micron regime poses considerable challenge to the conventional MOSFET structure. To suppress short-channel effects such as DIBL and V/sub t/ roll-off, extremely high levels of channel doping are required, but these result in increased leakage and degraded mobility. Simulation shows that the ultra-thin body MOSFET is a promising alternative structure that effectively suppresses DIBL and other short channel effects. The channel film thickness required is typically 30% of the gate length. The most difficult step for fabrication of the ultra-thin body FET is the formation of a uniform thin channel film. Oxidation and etch back have been proposed, but are limited by thickness uniformity of the starting SOI wafers and by process-induced variation. On the other hand, deposited films can be well controlled and have good uniformity, so finding ways to deposit highly uniform channel material is very plausible. Solid phase epitaxy (SPE) has been reported for fabrication of sub-100 nm devices (Subramanian et al, 1999). In SPE, the thin film is formed by lateral crystallization of an amorphous deposited silicon film, giving precise control over channel thickness. In this paper, 60 nm planarized SPEFETs with excellent performance are reported. The effect of different trench sizes is investigated. Both single sided and two sided crystallization on the channel film is also studied.

V. Subranmanian

Papers

60 nm planarized ultra-thin body solid phase epitaxy MOSFETs