A sanitary diaphragm valve is provided that includes a generally dome shaped diaphragm having a central boss that can be connected to or driven by a valve actuator. The diaphragm includes an outer peripheral edge and a relatively thin web portion that connects the boss to the outer edge. In one embodiment, the web portion is arcuate or dome shaped. The thinner web portion permits the diaphragm to have an extended cycle life and to permit the valve to operate at higher fluid pressures. The thin web may be defined by two different contoured surfaces, one convex and the other concave, such as formed by two radiuses. A valve body is provided that includes a bowl shaped valve cavity. This valve cavity includes an outer vertical edge to permit more thorough cleaning and to eliminate entrapment areas. The valve assembly provides support surfaces for the diaphragm that reduces stress on the diaphragm particularly at higher operating pressures. A deep bowl embodiment is provided in which the valve cavity is defined by a spherical and preferably a hemispherical surface with the cavity diameter being about the same as the diaphragm diameter. The diaphragm for the deep bowl design has a stem tip that seals one of the valve ports radially outward from the port. The port may include a chamfered valve seat adjacent the port, and the port may be formed by a conical bore.

Sanitary diaphragm valve

A precision operational amplifier operating in single supply mode, including a single differential transistor input pair and a cascoded CMOS transistor pair, stabilizes the drain-to-source voltage of the input transistor pair to ensure a stable off-set voltage and increased power supply and common mode rejection. The precision amplifier biases the cascoded CMOS transistor pair in accordance with the stabilized drain-to-source voltage of the differential transistor input pair. Such biasing may take the form of body biasing or biasing the gates of the cascode CMOS transistor pair to ensure that the CMOS transistor pair remain in the active region of operation when the common mode supply voltage approaches zero.

Operational amplifier output stage and method

A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is accomplished by using a low-bandwidth low-swing amplifier in the common mode feedback loop to improve the even-order harmonic performance in the signal path. The technique uses a separate multistage loop for the common mode feedback loop to attenuate the even-order harmonics. The common mode feedback loop is the fourth stage and uses the third stage of the nested Miller compensation circuit. The fourth stage of the common mode feedback loop includes a single harmonic and uses a low voltage supply to achieve lower power consumption by the common mode feedback loop.

Multistage common mode feedback for improved linearity line drivers

A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

Amplifier gain boost circuitry and method

A circuit including at least one low voltage input, at least one high voltage output, and a field transistor having a source, a drain and a control region. The circuit may comprise a high-voltage amplifier. In this embodiment, an electrical connection between the high-voltage output terminal and the field transistor control region, and an electrical connection between the input terminal and a second transistor. Various embodiments of the field transistor are described.

High voltage integrated circuit amplifier

A rail-to-rail differential amplifier includes first and second input terminals, and an output terminal and an input stage including differentially connected N-channel first and second input transistors, and differentially connected P-channel third and fourth input transistors. A P-channel first cascode transistor has a source coupled to a first supply voltage to the drain of the first input transistor. An N-channel cascode transistor has a source coupled by a second resistive element to a second supply voltage and to the drain of the third input transistor. A first gain boost amplifier has an output coupled to a gate of the first cascode transistor, a first input coupled to the source of the first cascode transistor and the drain of the first input transistor, and a second input coupled to a drain of the second input transistor and a bias control circuit. A second gain boost amplifier has an output coupled to a gate of the second cascode transistor, a first input coupled to the source of the second cascode transistor and to the drain of the third input transistor, and a second input coupled to a drain of the fourth input transistor and the bias control circuit. An output stage includes a pull-up transistor coupled between the first supply voltage and the output terminal, a pull-down transistor coupled between the second supply voltage and the output terminal, and a class AB bias circuit coupled between drain electrodes of the fist and second cascode transistors and between gate electrodes of the pull-up and pull-down transistors.

Rail-to-rail input / output operational amplifier and method

A precision voltage level shift circuit includes an emitter follower input circuit including a lateral PNP transistor having a base receiving an input voltage, and an emitter coupled to both an output terminal and a first current source. JFET is coupled between a collector of the input transistor and a first supply voltage conductor. A second PNP transistor has a base coupled to the collector of the first transistor and an emitter coupled to a second current source. A differential amplifier has a first input coupled to the output terminal, a second input coupled to the emitter of the second transistor, and an output coupled to the load element. The differential amplifier operates to maintain the voltage drop across the JFET at a level such that the emitter of the second PNP transistor is equal to the voltage of the emitter of the lateral PNP transistor to thereby maintain the collector-emitter voltage thereof at a constant value. Two of the voltage level shift circuits are used as input stages for an instrumentation amplifier.

Voltage level shifter and method

A three-stage amplifier including first, second, and third sequentially coupled stages is compensated without use of compensation capacitors, by applying an input signal to an input of the first stage and a first input of a first feed-forward stage, coupling an output signal of the first feed-forward stage to an output of the second stage, the second stage having an input coupled to an output of the first stage, coupling an output signal of the first stage to an input of a second feed-forward stage, coupling an output of the second feed-forward stage to an output of the third stage, coupling the input signal to an input of a third feed-forward stage, and coupling an output of the third feed-forward stage to the output of the third stage.

Circuit and technique for compensating high gain amplifier without compensation capacitors

An operational amplifier output circuit having a low, stable quiescent current includes an input stage (22) receiving an input voltage (vin ") and producing first (v1) and second (v2) signals. An output stage (23) includes a pull-up transistor (1) and a pull-down transistor (2), a base of the pull-up transistor (1) receiving the first signal (v1). An emitter of the pull-up transistor (1) is coupled by an output conductor (30) to a collector of the pull-down transistor (2). A base of the pull-down transistor is coupled to receive the second signal (v2), and an emitter of the pull-down transistor (2) is coupled to a second reference voltage conductor (GND). A feedback stage (24) includes a first sensing circuit (36) coupled to the pull-up transistor 1 and produces a third signal (v3) representing a collector current of the pull-up transistor (1), a second sensing circuit (37) coupled to the pull-down transistor (2) and producing a fourth signal (v4) representing a collector current of the pull-down transistor (2), a combining circuit (38) receiving the third (v3) and fourth (v4) signals to produce an error signal (v5) representing the larger of the third (v3) and fourth (v4) signals, and an error amplifier (17) receiving the error signal (v5) to produce a feedback signal (v6) regulating the first (v1) and second (v2) signals to establish a stable quiescent current in the pull-up transistor (1) or the pull-down transistor (2).

Operational amplifier push-pull output stage with low quiescent current

General approach to the design of the class AB output stages of bipolar and CMOS amplifiers based on common-mode negative feedback is discussed Frequency compensation of the result multiloop system is provided by feed forward links Effectiveness of the proposed method is shown on designs of rail-to-rail bipolar and CMOS output stages, all-NPN output stage, output stage of the hearing aids IC Common design mistakes are shown using industry-standard ICs

Vadim V. Ivanov

Papers

Rail-to-rail input / output operational amplifier and method

Voltage level shifter and method

Circuit and technique for compensating high gain amplifier without compensation capacitors

Operational amplifier push-pull output stage with low quiescent current

Class AB Output Stages of the Integrated Amplifiers