International Symposium on Quality Electronic Design

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects

The Effects of Substrates on 2D Crystals

This paper presents a design of fast voltage controlled delay element based on modified version of low noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to verify its performance.

/pdf/design-of-a-novel-current-balanced-voltage-controlled-delay-26q58jm17q.pdf

Design of a Novel Current Balanced Voltage Controlled Delay Element

This paper presents a voltage controlled delay buffer using a 2:1 multiplexer, designed in 0.35 μm CMOS process. The multiplexer is realized with transmission gate, which results in achievement of high speed, low power and full swing output characteristics of delay buffer. The least attained post layout rising edge delay is 120 ps that is comparable with standard cell inverter. The delay regulation range achieved over control voltage of 0 V to 3.3 V is from 120ps to 560ps. The performance of delay buffer for single edge delay control across PVT variations is successfully verified by design of modified delay lock loop.

Multiplexer based Voltage Controlled Delay Buffer Element

A 128-bin, 256 ns deep switched capacitor analog waveform sampling memory ASIC "Anusmriti" is designed using 500 MHz delay lock loop (DLL) in 0.7 um mixed CMOS process for sampling and storing the randomly occurring fast exponential signals. The stored memory samples can be read and digitized subsequently at lower rate thereby relieving the need of high speed digitization. The Anusmriti ASIC is designed specifically for pulse profile analysis of fast single shot events, occurring typically in High Energy Physics, Astronomy and laser/accelerator based experiments without using high frequency sampling clocks. This design incorporates 500 MHz delay locked loop, locked using a low frequency reference clock, so as to ensure good timing accuracy of each sampling interval at all the times. The Anusmriti ASIC has input dynamic range of 2 V and input capacitance of 64 pF. This full custom ASIC has been tested for equivalent sampling rate of 500 MHz with analog serial readout at 1 MHz. The ASIC features small bin spread across the memory depth. This paper describes design approach, trade-offs and test results of the Anusmriti ASIC. This ASIC occupies a die area of 5 mm by 3.5 mm.

500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti"

Over the years computers have played an essential part in the process of evolution of humans. This project approaches to attain an easy and efficient way of Human Computer Interaction using Gesture Recognition. This model would be able to behave as a mouse but will perform all functions of the mouse wirelessly thus making the device more portable and less complex. The main driving factors behind this project are Bluetooth technology, Gesture Recognition and Microcontroller. The Air Mouse will be a wireless and hand wearable device which will have varied applications. Many people who use the wired mouse often encounter a problem of strained fingers due to repeated use of mouse clicks, this inturn causes a medical condition known as Carpel Tunnel Syndrome, this wireless, wearable mouse reduces the risk of that device as well as can be very useful for handicapped people giving them an added edge in this fast paced and technology-oriented world. This model can also be used by lecturers and teachers while conducting lectures on projector and control basic functions of mouse using hand wearable device, in our model, we have proposed to add some Special Functions (Slide up, slide down, Left and Right click, Toggle between switches) which give an added edge to the device as it increases its functionality and practicality.

Air Mouse Using Bluetooth Technolgy

Challenges from interconnects in the deep sub-micron VLSI domain are now a days addressed through the new innovations. These are the materials based on graphene. Carbon Nanotubes and Graphene Nanoribbons are the two capable candidates to replace the traditional Cu in VLSI interconnect. In this paper we have reviewed the studies done till date on GNRs and their performance as interconnect in terms of delay, power dissipation and crosstalk.

Review of Graphene Nanoribbons

Challenges from interconnects in the deep submicron VLSI domain are now a days addressed through the new inventions. These inventions include device as well as interconnect technology domain. Materials based on Graphene such as Carbon Nanotubes and Graphene Nanoribbons are the two capable candidates to replace the traditional Cu in deep-nanometer VLSI interconnect. Multilayer graphene nanoribbon is making headway as an imminent nominee for deep-submicron regime interconnects with help of its properties like superior conductivity and high current carrying capabilities. FinFETs, the device with several gates are the most encouraging structure at device level in nano VLSI technology. In this research paper we have compared the performance of DIL system of conventional CMOS and MLGNR interconnects with DIL system of new device technology FinFET with MLGNR interconnect.

Analysis of Graphene Nanoribbon (GNR) interconnects with multi-gate device technology for VLSI applications

This paper presents a study of different digital circuits using two new technologies called GrapheneNanoribbon interconnects (GNRs) and FinFETs at 16 nm scale. A comparative study of the rise time and fall time is obtained at the output of the digital circuits designed using simple interconnects, using graphenenanoribbon interconnects (GNRs), and using FinFETs and GNR interconnects.

Vangmayee Sharda

Papers

500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti"

Air Mouse Using Bluetooth Technolgy

Review of Graphene Nanoribbons

Analysis of Graphene Nanoribbon (GNR) interconnects with multi-gate device technology for VLSI applications

Study of logic gates at 16nm with graphene nanoribbon interconnects and FinFETs