Proceedings of world academy of science, engineering and technology, vol 8

This book is about the Zynq-7000 All Programmable System on Chip, the family of devices from Xilinx that combines an application-grade ARM Cortex-A9 processor with traditional FPGA logic fabric Catering for both new and experienced readers, it covers fundamental issues in an accessible way, starting with a clear overview of the device architecture, and an introduction to the design tools and processes for developing a Zynq SoC Later chapters progress to more advanced topics such as embedded systems development, IP block design and operating systems Maintaining a 'real-world' perspective, the book also compares Zynq with other device alternatives, and considers end-user applications The Zynq Book is accompanied by a set of practical tutorials hosted on a companion website These tutorials will guide the reader through first steps with Zynq, following on to a complete, audio-based embedded systems design

The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc

The capacity of on-chip trace buffers employed for embedded logic analysis limits the observation window of a debug experiment. To increase the debug observation window, we propose a novel architecture for embedded logic analysis based on lossless compression. The proposed architecture is particularly useful for in-field debugging of custom circuits that have sources of nondeterministic behavior such as asynchronous interfaces. In order to measure the tradeoff between the area overhead and the increase in the observation window, we also introduce a new compression ratio metric. We use this metric to quantify the performance gain of three lossless compression algorithms suitable for embedded logic analysis.

On using lossless compression of debug data in embedded logic analysis

The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

An FPGA-based VLIW processor with custom hardware execution

New image and video coding standards have pushed the limits of compression by introducing new techniques with high computational demands. The Advanced Video Coder (ITU-T H.264, AVC MPEG-4 Part 10) is the last international standard, which introduces new enhanced features that require new levels of performance. Among the new tools present in AVC, the context-based binary arithmetic coder (CABAC) offers significant compression advantage over baseline entropy coders. CABAC is meant to be used in AVC's Main and High Profiles, which target broadcast and video storage and distribution of standard and high-definition contents. In these applications, hardware acceleration is needed as the computational load of CABAC is high, challenging programmable processors. Moreover, rate-distortion optimization (RDO) increases CABAC's load by two orders of magnitude. In this paper, we present a fast and new architecture for arithmetic coding adapted to the characteristics of CABAC, including optimized use of memory and context managing and fast processing able to encode more than two symbols per cycle. A maximum processing speed of 185 MHz has been obtained for 0.35 mu, able to encode high quality video in real time. Some of the proposed optimization may also be applied to software implementations obtaining significant improvements

High-Throughput Architecture for H.264/AVC CABAC Compression System

This paper investigates the algorithmic complexity of rate distortion optimization in the new H.264 video coding standard and proposes a hardware accelerator to reduce it by more than an order of magnitude. The accelerator incorporates an arithmetic coding engine and efficiently handles all the context information needed by RDO and CABAC in H.264. The bit stream generated by the CABAC engine is equivalent to that generated by the JM 9.4 reference software. The ISA of a controlling scalar RISC CPU has been extended with RDO/CABAC instructions and a implementation prototyped using state-of-the-art FPGA technology.

Harwdware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a processor-coprocessor architecture to reduce it by more than an order of magnitude. The proposed coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency via a low-complexity, multiplication-free, non-stalling, fully pipelined architecture. The coprocessor achieves a constant throughput for both coding and decoding processes of 1 symbol per cycle and is designed to be attached to a controlling embedded RISC CPU whose instruction set has been extended with arithmetic coding instructions.

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High-performance arithmetic coding VLSI macro for the H.264 video compression standard

We discuss the architecture definition and microarchitecture of a multi-standard, parametric vector accelerator for block-based video coding. Our target coding algorithms were the MPEG-2 TM5, MPEG-4 (XViD) and STM's proprietary H.264 implementation. We fully vectorized the MPEG-2 and MPEG-4 coders and partially vectorized the H.264 encoder. In the proprietary H.264 case, we targeted the inner loop of the motion estimation function. Our preliminary results demonstrate a significant complexity reduction of the order of 65%, 70% and 16% for MPEG-2, MPEG-4 and H.264 respectively. In the latter case the complexity of the inner loop of motion estimation has been reduced by 79% compared to the scalar case.

A multi-standard video coding accelerator based on a vector architecture

This paper describes a novel control system processor architecture based on DeltaSigma modulation known as the DeltaSigma -CSP. The DeltaSigma -CSP utilizes 1-bit processing which is a new concept in digital control applications with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional-negate-and-add (CNA) unit is instead used for operations in control law implementations. For this reason, the proposed processor has a very small silicon footprint and runs at very high frequencies making it ideal for high-sampling rate, real-time control applications. A number of DeltaSigma -CSP configurations have been implemented as VLSI hard macros in a high-performance 0.13-mum CMOS process and a particular configuration achieved a post-route operating frequency of 355 MHz resulting in a 2.17 MHz sampling rate for a fourth-order control law implementation. Additional results prove that the DeltaSigma -CSP compares very favorably, in terms of silicon area and sampling rates, to two other specialized digital control processing systems, including direct, hardwired implementation of control laws; at the same time, it substantially outperforms software implementations of control laws running on very wide, general-purpose VLIW architectures.

A Novel $\Delta\Sigma$ Control System Processor and Its VLSI Implementation

A new genetic algorithm, termed the ‘optimum individual monogenetic genetic algorithm’ (OIMGA), is presented whose properties have been deliberately designed to be well suited to hardware implementation. Specific design criteria were to ensure fast access to the individuals in the population, to keep the required silicon area for hardware implementation to a minimum and to incorporate flexibility in the structure for the targeting of a range of applications. The first two criteria are met by retaining only the current optimum individual, thereby guaranteeing a small memory requirement that can easily be stored in fast on-chip memory. Also, OIMGA can be easily reconfigured to allow the investigation of problems that normally warrant either large GA populations or individuals many genes in length. Local convergence is achieved in OIMGA by retaining elite individuals, while population diversity is ensured by continually searching for the best individuals in fresh regions of the search space. The results given in this paper demonstrate that both the performance of OIMGA and its convergence time are superior to those of a range of existing hardware GA implementations. Keywords—Genetic algorithms, genetic hardware, machine learning.

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Vassilios Chouliaras

Papers

Harwdware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

High-performance arithmetic coding VLSI macro for the H.264 video compression standard

A multi-standard video coding accelerator based on a vector architecture

A Novel $\Delta\Sigma$ Control System Processor and Its VLSI Implementation

A Novel Genetic Algorithm Designed for Hardware Implementation