An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The silicon-based microelectronics industry is rapidly approaching a point where device fabrication can no longer be simply scaled to progressively smaller sizes. Technological decisions must now be made that will substantially alter the directions along which silicon devices continue to develop. One such challenge is the need for higher permittivity dielectrics to replace silicon dioxide, the properties of which have hitherto been instrumental to the industry's success. Considerable efforts have already been made to develop replacement dielectrics for dynamic random-access memories. These developments serve to illustrate the magnitude of the now urgent problem of identifying alternatives to silicon dioxide for the gate dielectric in logic devices, such as the ubiquitous field-effect transistor.

Alternative dielectrics to silicon dioxide for memory and logic devices

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias Then the wafer back side is etched until the metal is exposed When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (eg silicon) Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder In some embodiments, the wafer is diced and the dice are tested before the etch The etch and the deposition of the additional dielectric are performed on good dice only In some embodiments, the dice are not used for vertical integration

Integrated circuits and methods for their fabrication

A system and method for determining preferred configuration settings and sets of possible positions (801-806) for wireless or wired network equipment (501) includes a site-specific network model used with adaptive processing of predicted or measured parameters to perform efficient design and ongoing management of network performance, the equipment having data and settings associated therewith. A secure wireless communication system in a physical environment (3200) includes a display for displaying a site-specific representation of the environment, a plurality of wireless communication components (3202,3203) positioned at a plurality of location within the environment, and an indicator for identifying the presence of a possible intruder or intruder devices (2700) in the environment.

System and method for automated placement or configuration of equipment for obtaining desired network performance objectives and for security, RF tags, and bandwidth provisioning

A display has a first array of pixels connected to emit individually-controlled amounts of light onto a second array of pixels. The second array of pixels is connected to pass individually-controllable portions of the light. The display has a controller connected to control the pixels of the first and second arrays of pixels. The controller is configured to control the pixels of the first array of pixels to provide on the second array of pixels an approximation of an image specified by image data; determine a difference between the image and the approximation of the image at individual pixels of the second array of pixels; and control the pixels of the second array of pixels to modulate the approximation of the image according to the corresponding determined differences.

High dynamic range display devices

An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.

Method for forming a storage cell capacitor compatible with high dielectric constant materials

The present invention develops a container capacitor by forming a first insulative layer over conductive word lines; forming an opening between neighboring conductive word lines; forming a conductive plug between neighboring parallel conductive word lines; forming a planarized blanketing second insulating layer over the first insulative layer and the conductive plug; forming an opening into the second insulating layer, the opening thereby forming a container shape; forming a conductive spacer adjacent the wall of the container form, the conductive spacer having inner and outer surfaces; removing the second insulating layer, thereby exposing the outer surface of the conductive spacer; forming a layer of hemispherical grained conductive material superjacent the inner and outer surfaces of the conductive spacer; forming insulating spacers adjacent the inner and outer surfaces of the hemispherical grained conductive material; patterning the hemispherical grained conductive material to form a separate conductive container structure serving as a first capacitor cell plate; removing the insulating spacers; forming a capacitor cell dielectric layer adjacent and coextensive the conductive container structure and the first insulating layer; and forming a second conductive layer superjacent and coextensive the capacitor cell dielectric layer, the second conductive layer forming a second capacitor cell plate The process of the present invention can be further modified to form a DRAM double container capacitor storage cell

Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node

Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed over the layer of polycrystalline silicon thereby leaving protected and exposed poly. The exposed polycrystalline silicon is doped, then oxidized, with the protected poly being free of oxidation. The nonoxidizing layer is stripped, and a blanket implant is performed. The oxidation prevents the previously doped polycrystalline silicon from being counterdoped. The oxidation is then stripped and wafer processing continues. In a second embodiment, a layer of resist is formed over the polycrystalline silicon layer, and the exposed poly is heavily doped with a material having a first conductivity type. The resist is removed, and the surface is blanket doped with a material having a second conductivity type. The second conductivity type is chosen so as to have minimal counterdoping effect of the previously doped polycrystalline silicon. Wafer processing continues.

Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device

A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.

Oxidation enhancement in narrow masked field regions of a semiconductor wafer

A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590° and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm 2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.

Viju K. Mathews

Papers

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node

Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device

Oxidation enhancement in narrow masked field regions of a semiconductor wafer

Method of forming a capacitor in semiconductor wafer processing