Reconfigurable Computing. Accelerating Computation with Field-Programmable Gate Arrays by Maya B. Gokhale and Paul S. Graham Springer, 2005, 238 pp. ISBN-13 978-0387-26105-8, $87.20 Reconfigurable Computing Accelerating Computation with Field-Programmable Gate Arrays is an expository and easy to digest book. The authors are recognized leaders with many years of experience on the field of reconfigurable computing. The book is written so that non-specialists can understand the principles, techniques and algorithms. Each chapter has many excellent references for interested readers. It surveys methods, algorithms, programming languages and applications targeted to reconfigurable computing. Automatic generation of parallel code from a sequential program on conventional micro-processor architectures remains an open problem. Nevertheless, a wide range of computationally intensive applications have benefited from many tools developed to tackle such a problem. For RC, it is even a much harder problem (perhaps 10x and up) and intense research is being devoted to make RC a common-place practical tool. The aim of the authors is threefold. First, guide the readers to know current issues on HLL for RC. Second, help the readers understand the intricate process of algorithmic-to-hardware compilation. And third, show that, even though this process is painful, if the application is suitable for RC the gains in performance are huge. The book is divided into two parts. The first part contains four chapters about reconfigurable computing and languages. Chapter 1 presents an introduction of RC, contrasting conventional fixed instruction microprocessors with RC architectures. This chapter also contains comprehensive reference material for further reading. Chapter 2 introduces reconfigurable logic devices by explaining the basic architecture and configuration of FPGAs. Chapter 3 deals with RC systems by discussing how parallel processing is achieved on reconfigurable computers and also gives a survey of RC systems today. Then, in chapter 4, languages, compilation, debugging and their related manual vs. automatic issues are discussed. The second part of the book comprises five chapters about applications of RC. Chapter 5 and 6 discuss digital signal and image processing applications. Chapter 7 covers the application of RC to secure network communications. The aim of Chapter 8 is to discuss some important bioinformatics applications for which RC is a good candidate, their algorithmic problems and hardware implementations. Finally, Chapter 9 covers two applications of reconfigurable supercomputers. The first one is a simulation of radiative heat transfer and the second one models large urban road traffic. This book is neither a technical nor a text book, but in the opinion of this reviewer, it is an excellent state-of-the-art review of RC and would be a worthwhile acquisition by anyone seriously considering speeding up a specific application. On the downside, it is somewhat disappointing that the book does not contain more information about HLL tools that could be used to help close the gap between traditional HPC community and the raw computing power of RC. Edusmildo Orozco, Department of Computer Science, University Of Puerto Rico at Rio Piedras.

Reconfigurable Computing. Accelerating Computation with Field-Programmable Gate Arrays

This work presents a case study in the oil and gas industry, namely the FPGA implementation of the 2D reverse timing migration (RTM) seismic modeling algorithm. These devices have been largely used as accelerators in scientific computing applications that require massive data processing, large parallel machines, huge memory bandwidth and power. The RTM algorithm enables you to directly solve the acoustic and elastic waves problems with precision in complex geological structures, demanding a high computational power. To face such challenges we suggest strategies such as reduced arithmetic precision, based on fixed-point numbers, and a highly parallel architecture are suggested. The effects of such reduced precision for storage/processing data are analyzed in this chapter through signal-noise ratio (SRN) and universal image quality index (UIQI) metrics. The results show that SRN higher than 50dB can be considered acceptable for a migrated image with 15 bits word size. A special stream-processing architecture aiming to implement the best possible data reuse for the algorithm is also presented. It was implemented by an FIFO-based cache in the internal memory of the FPGA. A temporal pipeline structure has also been developed, allowing that multiple time steps to be performed at the same time. The main advantage of this approach is the ability to keep the same memory bandwidth needs of processing just one time step. The number of time steps processed at the same time is limited by the amount of FPGA internal memory and logic blocks. The algorithm was implemented on an Altera Stratix 260E, with 16 processing elements (PEs). The FPGA was 29 times faster than the CPU and only 13% slower than the GPGPU. In terms of power consumption, the CPU+FPGA was 1.7 times more efficient than the GPGPU system.

High Performance Implementation of RTM Seismic Modeling on FPGAs: Architecture, Arithmetic and Power Issues

Modern-day High Performance Computing (HPC) trends are shifting towards exascale performance figures in order to satisfy the needs of many compute-intensive and power-hungry applications. Hence, the European-funded ECOSCALE project introduces a highly innovative architecture, which spreads the workload among a number of independent and concurrently-operating conventional (CPU) as well as reconfigurable (FPGA) processing elements that execute OpenCL cores whilst significantly minimizing the need for data transfers. The accelerator cores implemented on the ECOSCALE platform correspond to the project use cases and have been the source of a meticulous exploration process for optimal performance results such as execution time. This paper focuses on performance and power optimizations of the Michelsen algorithm. This algorithm is an efficient calculator of the Rachford-Rice equation, which is extensively used in the field of oil Reservoir Simulation (RS). The algorithm was first optimized manually through Vivado HLS and, subsequently, using a Design Space Exploration (DSE) tool we developed in [1]. Here we present up-to-date optimization results based on the latest FPGA ECOSCALE platform in order to reveal bottlenecks, saturation points and design alternatives. The measurements are performed on real data and the evaluation results register significant gains in calculation times over conventional CPU platforms; an achievement that carries added value considering the significantly reduced power consumption costs commonly associated with reconfigurable hardware.

Optimized FPGA Implementation of a Compute-Intensive Oil Reservoir Simulation Algorithm

The recent increase in computing power of FPGAs has allowed its use in areas such as seismic data processing. Additionally, besides the capability of performing computations in parallel way, FPGAs also support application-specific number representations. In this type of application, in order to achieve better performance, instead of using the floating-point standard, usually the processing and storage of data is done using the fixed point standard. However, the change of representation can cause a degradation in the quality of the results. In the petroleum industry, a seismic image of poor quality can represent an erroneous interpretation of the subsurface, resulting in catastrophic losses. For this reason, it is essential that the quality of data obtained from the seismic data processing for low precision can be evaluated within reliable technical criteria. In this paper, a real case study was used in order to evaluate the efficiency of two different metrics applied to this seismic application based on RTM algorithm. The main strategy is to explore the precision reduction in terms of SNR (Signal-to-Noise Ratio) and UIQI (Universal Image Quality Index) metrics, in order to improve the performance of the system. Results show a performance gain of 50% compared with the architecture implemented in hardware using floating point standart IEE754.

Vinicius V. Brito

Papers

Performance Evaluation Model based on Precision Reduction and FPGAs Applied to Seismic Modeling