The basic problem of high-level synthesis is the mapping of a behavioral description of a digital system into an RTL design consisting of a data path and a control unit. The authors introduce the FSMD model, which forms the basis for synthesis. They discuss the main considerations in a high-level synthesis environment: the input description language, the internal representation, and the main synthesis tasks-allocation, scheduling, and binding. They conclude with some problems that must be solved to make high-level synthesis a widely accepted methodology. >

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An Introduction to High-Level Synthesis

We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.

Data and memory optimization techniques for embedded systems

https://ir.nctu.edu.tw:443/bitstream/11536/10064/1/000251483200003.pdf

Reconfiguring the innovation policy portfolios for Taiwan's SIP Mall industry

Rising complexities and performances of integrated circuits and systems, shortening time-to-market demands for electronic equipments, growing installed bases of intellectual property (IP), requirements for adapting existing IP blocks with new services, all stress high-level design as a prominent research topic and call for the development of appropriate methodological solutions. In this aim, system design based on the so-called "synchronous hypothesis" consists of abstracting the nonfunctional implementation details of a system and lets one benefit from a focused reasoning on the logics behind the instants at which the system functionalities should be secured. With this point of view, synchronous design models and languages provide intuitive (ontological) models for integrated circuits. This affinity explains the ease of generating synchronous circuits and verify their functionalities using compilers and related tools that implement this approach. In the relational mathematical model behind the design language SIGNAL, this affinity goes beyond the domain of purely synchronous circuits, and embraces the context of complex architectures consisting of synchronous circuits and desynchronization protocols: globally asynchronous and locally synchronous architectures (GALS). The unique features of the relational model behind SIGNAL are to provide the notion of polychrony: the capability to describe circuits and systems with several clocks; and to support refinement: the ability to assist and support system design from the early stages of requirement specification, to the later stages of synthesis and deployment. The SIGNAL model provides a design methodology that forms a continuum from synchrony to asynchrony, from specification to implementation, from abstraction to concretization, from interfaces to implementations. SIGNAL gives the opportunity to seamlessly model circuits and devices at multiple levels of abstractions, by implementing mechanisms found in many hardware simulators, while reasoning within a simple and formally defined mathematical model. In the same manner, the flexibility inherent to the abstract notion of signal, handled in the synchronous-desynchronized design model of SIGNAL, invites and favors the design of correct by construction systems by means of well-defined transformations of system specifications (morphisms) that preserve the intended semantics and stated properties of the architecture under design. The aim of the present article is to review and summarize these formal, correct-by-construction, design transformations. Most of them are implemented in the POLYCHRONY tool-set, allowing for a mixed bottom–up and top–down design of an embedded hardware–software system using the SIGNAL design language.

/pdf/polychrony-for-system-design-1cwj0o6epa.pdf

Polychrony for system design

Efficient utilization of on-chip memory space is extremely important in modern embedded system applications based on processor cores. In addition to a data cache that interfaces with slower off-chip memory, a fast on-chip SRAM, called Scratch-Pad memory, is often used in several applications, so that critical data can be stored there with a guaranteed fast access time. We present a technique for efficiently exploiting on-chip Scratch-Pad memory by partitioning the application's scalar and arrayed variables into off-chip DRAM and on-chip Scratch-Pad SRAM, with the goal of minimizing the total execution time of embedded applications. We also present extensions of our proposed memory assignment strategy to handle context switching between multiple programs, as well as a generalized memory hierarchy. Our experiments on code kernels from typical applications show that our technique results in significant performance improvements.

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On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems

During synthesis of behavioral descriptions array variables are implemented with memory modules In this paper we show that simple one-to-one mapping between the array variables and the memory modules lead to inefficient designs We propose a new algorithm, MeSA, which computes for a given set of array variables, (a) the number of memory modules, (b) the size of each module (c) the number of ports on each module and (d) and the grouping of array variables assigned to each memory module The effects of address translations are incorporated into the algorithm While most previous research efforts have concentrated on scalar variables, the primary focus in this paper is deriving efficient storage assignment for array variables >

An algorithm for array variable clustering

Most synthesis systems generate designs from hardware descriptions by relating each language construct to a particular hardware structure. Thus, designs obtained from these systems are dependent on description styles. In other words, semantically equivalent descriptions with different orderings or groupings of conditional and assignment statements could generate designs with distinctively different costs and performance. This paper introduces an approach for minimizing the syntactic variance of different description styles. Experimental data on several examples shows the effectiveness of the proposed approach.

High-Level Transformations for Minimizing Syntactic Variances

With widespread recent emphasis on System-On-a-Chip (SOC), IP reuse has emerged as a vital and growing business in semiconductor industry. In this paper, we will address essential issues for IP reuse by discussing current challenges to the success of IP businesses and identifying the obstacles that need to be overcome.

Essential issues for IP reuse

The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for macrocells (PLAs), the proposed models formulate layout area as a function of transistors and routing tracks which can be computed in O(n log n) time complexity, where n is the number of nets in the netlist. This allows one to explore design space in high-level synthesis rapidly and efficiently. The authors have tested their layout models on the widely used elliptic-filter benchmark. The results show that these models can more accurately predict layout areas than models based on the number and size of registers and multiplexers. >

/pdf/layout-area-models-for-high-level-synthesis-4hhbizjhd1.pdf

Layout-area models for high-level synthesis

With widespread recent emphasis on System-Ona-Chip (SOC), IP reuse has emerged as a vital and growing business in semiconductor industry. In this paper, we will address essential issues for IP reuse by discussing current challenges to the success of IP businesses and identifying the obstacles that need to be overcome.

Viraphol Chaiyakul

Papers

An algorithm for array variable clustering

High-Level Transformations for Minimizing Syntactic Variances

Essential issues for IP reuse

Layout-area models for high-level synthesis

Embedded tutorial: essential issues for IP reuse