Computational geometry is concerned with the design and analysis of algorithms for geometrical problems. In addition, other more practically oriented, areas of computer science— such as computer graphics, computer-aided design, robotics, pattern recognition, and operations research—give rise to problems that inherently are geometrical. This is one reason computational geometry has attracted enormous research interest in the past decade and is a well-established area today. (For standard sources, we refer to the survey article by Lee and Preparata [19841 and to the textbooks by Preparata and Shames [1985] and Edelsbrunner [1987bl.) Readers familiar with the literature of computational geometry will have noticed, especially in the last few years, an increasing interest in a geometrical construct called the Voronoi diagram. This trend can also be observed in combinatorial geometry and in a considerable number of articles in natural science journals that address the Voronoi diagram under different names specific to the respective area. Given some number of points in the plane, their Voronoi diagram divides the plane according to the nearest-neighbor

Voronoi diagrams—a survey of a fundamental geometric data structure

Models and Methods in Social Network Analysis presents the most important developments in quantitative models and methods for analyzing social network data that have appeared during the 1990s. Intended as a complement to Wasserman and Faust’s Social Network Analysis: Methods and Applications, it is a collection of original articles by leading methodologists reviewing recent advances in their particular areas of network methods. Reviewed are advances in network measurement, network sampling, the analysis of centrality, positional analysis or blockmodeling, the analysis of diffusion through networks, the analysis of affiliation or “two-mode” networks, the theory of random graphs, dependence graphs, exponential families of random graphs, the analysis of longitudinal network data, graphic techniques for exploring network data, and software for the analysis of social networks.

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Models and methods in social network analysis

This book provides an up-to-date account of RNSs and arithmetic. It covers the underlying mathematical concepts of RNSs; the conversion between conventional number systems and RNSs; the implementation of arithmetic operations; various related applications are also introduced. In addition, numerous detailed examples and analysis of different implementations are provided.

Residue Number Systems: Theory and Implementation

Neural Networks (NN) are a family of models for a broad range of emerging machine learning and pattern recondition applications. NN techniques are conventionally executed on general-purpose processors (such as CPU and GPGPU), which are usually not energy-efficient since they invest excessive hardware resources to flexibly support various workloads. Consequently, application-specific hardware accelerators for neural networks have been proposed recently to improve the energy-efficiency. However, such accelerators were designed for a small set of NN techniques sharing similar computational patterns, and they adopt complex and informative instructions (control signals) directly corresponding to high-level functional blocks of an NN (such as layers), or even an NN as a whole. Although straightforward and easy-to-implement for a limited set of similar NN techniques, the lack of agility in the instruction set prevents such accelerator designs from supporting a variety of different NN techniques with sufficient flexibility and efficiency.In this paper, we propose a novel domain-specific Instruction Set Architecture (ISA) for NN accelerators, called Cambricon, which is a load-store architecture that integrates scalar, vector, matrix, logical, data transfer, and control instructions, based on a comprehensive analysis of existing NN techniques. Our evaluation over a total of ten representative yet distinct NN techniques have demonstrated that Cambricon exhibits strong descriptive capacity over a broad range of NN techniques, and provides higher code density than general-purpose ISAs such as ×86, MIPS, and GPGPU. Compared to the latest state-of-the-art NN accelerator design DaDianNao [5] (which can only accommodate 3 types of NN techniques), our Cambricon-based accelerator prototype implemented in TSMC 65nm technology incurs only negligible latency/power/area overheads, with a versatile coverage of 10 different NN benchmarks.

Cambricon: an instruction set architecture for neural networks

Evolvable hardware (EHW) has attracted increasing attention since the early 1990s with the advent of easily reconfigurable hardware, such as field programmable gate arrays (FPGAs). It promises to provide an entirely new approach to complex electronic circuit design and new adaptive hardware. EHW has been demonstrated to be able to perform a wide range of tasks, from pattern recognition to adaptive control. However, there are still many fundamental issues in EHW that remain open. This paper reviews the current status of EHW, discusses the promises and possible advantages of EHW, and indicates the challenges we must meet in order to develop practical and large-scale EHW.

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Promises and challenges of evolvable hardware

This paper presents new, fast hardware for computing the exponential function, sine, and cosine. The main new idea is to use low-precision arithmetic components to approximate high precision computations, and then to correct very quickly the approximation error periodically so that the effect is to get high precision computation at near low-precision speed. The algorithm used in the paper is a nontrivial modification of the well-known CORDIC algorithm, and might be applicable to the computation of other functions than the ones presented.

On hardware for computing exponential and trigonometric functions

The author presents a very fast adder for double-precision mantissas, which is an improvement on T. Lynch and E. E. Swartzlandes, Jr.'s spanning tree carry lookahead adder or redundant cell adder (see ibid., vol. 41, 1992) which was implemented using the Am29050 microprocessor. The adder presented is faster than theirs mainly because Manchester carry chains of various lengths are used instead of chains all of the same length. >

A recursive carry-lookahead/carry-select hybrid adder

The author shows how to design one-level carry-skip adders that attain very high speeds. One-level carry-skip adders are very fast adders that are hardly more complex than the much-slower ripple adders. The design procedure allows the use of realistic component delays obtained by simulation and is technology-independent. An example of a 64-b, 1 mu m CMOS adder is given. This adder achieves an add time of 6.23 ns, measured by SPICE simulation with realistic loads. This delay figure excludes sum buffering delays, which depend on the particular application of the adder. The combination of high-speed and simplicity makes one-level carry-skip adders attractive for applications in highly parallel systems. >

Designing optimum one-level carry-skip adders

This paper describes a new type of carry-skip adder, which can be faster than the conventional two-level carry-skip adders. A way to design optimum adders of this new type is described. In optimum adders of this type, the sizes of the sections of bit positions are bimodal, but the sizes of the blocks in each section are unimodal, unlike the bimodal block sizes in Guyot et al.'s traditional two-level carry-skip adders. A 60-b 2- mu m CMOS adder of this type is designed. This adder's simulated delay is approximately 12.6 ns. >

Accelerated two-level carry-skip adders-a type of very fast adders

A new modified Manchester carry chain (MCC) is presented. The objective is to reduce the carry propagation delay in the chain obtaining a layout-oriented architecture. The modification provides bypass (carry-skip) routes for the carry to propagate through quickly, avoiding long carry propagation paths that go through the entire carry chain. When realised using AMS 0.35 μm 2-poly 3-metal 3.3V CMOS technology (CSD), a 32-bit adder designed as described here shows a computational delay of about 2.2 ns and an energy dissipation of only 27 pJ. This represents a significant improvement in terms of energy–delay product with respect to both conventional MCC adders and newer adder structures.

Vitit Kantabutra

Papers

On hardware for computing exponential and trigonometric functions

A recursive carry-lookahead/carry-select hybrid adder

Designing optimum one-level carry-skip adders

Accelerated two-level carry-skip adders-a type of very fast adders

Fast and energy-efficient Manchester carry-bypass adders