The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efficient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.

Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications

A significant amount of research in the field of stereo vision has been published in the past decade. Considerable progress has been made in improving accuracy of results as well as achieving real-time performance in obtaining those results. This work provides a comprehensive review of stereo vision algorithms with specific emphasis on real-time performance to identify those suitable for resource-limited systems. An attempt has been made to compile and present accuracy and runtime performance data for all stereo vision algorithms developed in the past decade. Algorithms are grouped into three categories: (1) those that have published results of real-time or near real-time performance on standard processors, (2) those that have real-time performance on specialized hardware (i.e. GPU, FPGA, DSP, ASIC), and (3) those that have not been shown to obtain near real-time performance. This review is intended to aid those seeking algorithms suitable for real-time implementation on resource-limited systems, and to encourage further research and development of the same by providing a snapshot of the status quo.

Review of stereo vision algorithms and their suitability for resource-limited systems

This paper describes a new architecture and the corresponding implementation of a stereo vision system that covers the entire stereo vision process including noise reduction, rectification, disparity estimation, and visualization Dense disparity estimation is performed using the non-parametric rank transform and semi-global matching (SGM), which is among the top performing stereo matching methods and outperforms locally-based methods in terms of quality of disparity maps and robustness under difficult imaging conditions Stream-based processing of the SGM despite its non-scan-aligned, complex data dependencies is achieved by a scalable, systolic-array-based architecture This architecture fulfills the demands of real-world applications regarding frame rate, depth resolution and low resource usage The architecture is based on a novel two-dimensional parallelization concept for the SGM An FPGA implementation on a Xilinx Virtex-5 generates disparity maps of VGA images (640×480 pixel) with a 128 pixel disparity range under real-time conditions (30 fps) at a clock frequency as low as 39 MHz

Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation

We use a coplanar QCA crossover architecture in the design of QCA full adders that leads to reduction of QCA cell count and area consumption without any latency penalty. This crossover uses non-adjacent clock zones for the two crossing wires. We further investigate the impact of these gains on carry flow QCA adders. These designs have been realized with QCADesigner, evaluated, and tested for correctness. For better performance comparison with previous relevant works, we use a QCA-specific cost function, as well as the conventional evaluation method. We show 23% cell count and 48% area improvements over the best previous QCA full adder design. Similar results for 4-, 8-, 16-, 32-, and 64-bit adders are 29% (22%), 24% (51%), 19% (54%), 13% (69%), and 9% (49%) cell count reduction (less area consumption), respectively.

Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover

This report describes the progress made towards the completion of a specific task on error-correcting coding. The proposed research consisted of investigating the use of modulation block codes as the inner code of a concatenated coding system in order to improve the overall space link communications performance. The study proposed to identify and analyze candidate codes that will complement the performance of the overall coding system which uses the interleaved RS (255,223) code as the outer code.

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Error-correction coding

In this brief, a new low-power level shifter (LS) is presented for robust logic voltage shifting from near/sub-threshold to above-threshold domain. The new circuit combines the multi-threshold CMOS technique along with novel topological modifications to guarantee a wide voltage conversion range with limited static power and total energy consumption. When implemented in a 90-nm technology process, the proposed design reliably converts 180-mV input signals into 1-V output signals, while maintaining operational frequencies above 1-MHz, also taking into account process-voltage-temperature variations.Post-layout simulation results demonstrate that the new LS reaches a propagation delay less than 22 ns, a static power dissipation of only 6.4 nW, and a total energy per transition of only 74 fJ for a 0.2-V 1-MHz input pulse.

Low-Power Level Shifter for Multi-Supply Voltage Designs

Multisupply voltage design technique is widely used in modern system-on-chips to tradeoff energy and speed. Level shifters (LSs) allow different voltage domains to be interfaced. In this brief, a new LS is presented for fast and wide range voltage conversion. Because of a novel architecture combined with the use of multithreshold CMOS technique, the proposed circuit guarantees robust voltage shifting from the deep subthreshold to the above-threshold domain while exhibiting fast response and low energy consumption. When implemented in a 90-nm technology node, considering process-voltage-temperature variations, the proposed design reliably converts 100-mV input signals into 1 V output signals. Post-layout simulation results demonstrate that the new LS shows a propagation delay of 16.6 ns, a static power dissipation of 8.7 nW and a total energy per transition of only 77 fJ for a 0.2 V 1-MHz input pulse.

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this brief, we propose a new adder that outperforms all state-of-the-art competitors and achieves the best area-delay tradeoff. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. The 64-bit version of the novel adder spans over 18.72 μ2 of active area and shows a delay of only nine clock cycles, that is just 36 clock phases.

Area-Delay Efficient Binary Adders in QCA

A high-performance fully reconfigurable FPGA-based 2D convolution processor

An efficient technique for designing high-performance logic circuits operating in sub-threshold region is proposed. A simple gate-level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency.

Stefania Perri

Papers

Low-Power Level Shifter for Multi-Supply Voltage Designs

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

Area-Delay Efficient Binary Adders in QCA

A high-performance fully reconfigurable FPGA-based 2D convolution processor

Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates