Showing papers by "Vivek Tiwari published in 2016"

Power Analysis and Optimization from Circuit to Register-Transfer Levels

Abstract: This chapter provides an overview of the most significant computer-aided design (CAD) techniques proposed for low power. It describes the issues and methods for power estimation at different levels of abstraction, thus defining the targets for the tools. The chapter reviews power optimization techniques at the circuit and logic levels of abstraction respectively. It suggests that the reader to the Register-Transfer Levels power analysis and optimization techniques for more details on the voltage island technique. The variable voltage and voltage-island techniques are complementary and can be implemented on the same block and used simultaneously. Static power analysis is typically performed using the sub-threshold model to estimate leakage per micron of gate width of a minimum-length transistor. Then that model is extended to estimate leakage over the entire chip. Most of the research for CAD tools targets system or architectural level optimization, which potentially have a higher overall impact, given the breadth of their application.