M
Massimo Poncino
Researcher at Polytechnic University of Turin
Publications - 432
Citations - 6341
Massimo Poncino is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 38, co-authored 407 publications receiving 5865 citations. Previous affiliations of Massimo Poncino include Seoul National University & Commissariat à l'énergie atomique et aux énergies alternatives.
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Proceedings ArticleDOI
A discrete-time battery model for high-level power estimation
TL;DR: A discrete-time model for the complete power supply sub-system that closely approximates the behavior of its circuit-level (i.e., HSpice), continuous-time counterpart is introduced and can be successfully used for the purpose of battery life-time estimation during design optimization.
Journal ArticleDOI
Discrete-time battery models for system-level low-power design
TL;DR: A discrete-time model for the complete power supply subsystem that closely approximates the behavior of its circuit-level continuous-time counterpart and is abstract and efficient enough to enable event-driven simulation of digital systems described at a very high level of abstraction.
Journal ArticleDOI
SystemC cosimulation and emulation of multiprocessor SoC designs
TL;DR: The authors describe a simulation environment that targets heterogeneous multiprocessor systems and is currently working to extend their methodology to more complex on-chip architectures.
Proceedings ArticleDOI
Selective instruction compression for memory energy reduction in embedded systems
TL;DR: A number of decompression schemes and architectures are described that effectively trade hardware complexity for memory energy and bandwidth reduction, as proved by experimental data collected by executing several sample programs.
Journal ArticleDOI
Power optimization of core-based systems by address bus encoding
TL;DR: Data concerning the quality and the performance of the automatically synthesized encoding/decoding circuits, as well as the results obtained for a realistic core-based design, indicate the practical usefulness of the proposed power optimization strategy.