An apparatus and method for high speed phase modulation of optical beam with reduced optical loss. In one embodiment, an apparatus includes a first region of an optical waveguide disposed in semiconductor material. The first region has a first conductivity type. The apparatus also includes a second region of the optical waveguide disposed in the semiconductor material. The second region has a second conductivity type opposite to the first conductivity type. A first contact is included in the apparatus and is coupled to the optical waveguide at a first location in the first region outside an optical path of an optical beam to be directed through the optical waveguide. The apparatus also includes a first higher doped region included in the first region and coupled to the first contact at the first location to improve an electrical coupling between the first contact and the optical waveguide. The first higher doped region has a higher doping concentration than a doping concentration within the optical path.

Method and apparatus for phase shifting an optical beam in an optical device

The invention relates to a semiconductor device and to a method of fully eliminating lattice defects in N-conductive zones of a semiconductor device which are generated by ion implantation of phosphorus. According to the invention, conductivity-determining ions like antimony or arsenic are implanted into phosphorus-doped zones of a semi-conductor device. A dosage of 1 to 10% of the phosphorus dose is used. The implantation of the antimony or arsenic takes place with the same, or with a greater implantation depth than the phosphorus depth. Subsequent to the antimony/arsenic implantation the device is annealed in an inert gas atmosphere at approximately 1000° C.

Method of eliminating lattice defects in a semiconductor device

A bias voltage generation circuit comprises a bias voltage generation portion having a bias control node, a first switching unit, and a second switching unit. The bias voltage generation portion is used to generate a bias voltage of a predetermined potential and supply the bias voltage to an ECL circuit during an operation period, and the first switching unit is used to drop the bias voltage during a standby period in response to a bias voltage control signal. The second switching unit is used to switch OFF during the standby period to cut off a current flow through the bias control node and switch ON during the operation period to supply a current through the bias control node in response to the bias voltage control signal. Consequently, a current flow during the standby period can be reduced, and power consumption of the bias voltage generation circuit during the standby period is minimal.

Bias voltage generation circuit of ecl level for decreasing power consumption thereof

A semiconductor substrate is coated with an insulating film followed by a layer of polysilicon. The polysilicon layer is coated with a non-oxidizable mask, such as silicon nitride, and then oxidized to convert the exposed regions to silicon oxide and add further thickness to the converted oxide regions. When the mask is removed, the thicker silicon oxide regions serve as an in situ mask for selectively implanting impurity ions through the thinner polysilicon regions and into the semiconductor substrate. When the silicon oxide regions are etched away, the remaining polysilicon regions serve as an ion implantation mask for permitting selective ion implantation through the voids left by etching the silicon oxide regions.

Method of patterning polysilicon

A method is disclosed to implant layers in semiconductor substrates with asymmetrical edges, that is, one edge slopes towards the surface of the substrate and the other terminates abruptly inside the bulk. The method involves using lift-off techniques to make ion-stopping masks with near-vertical sidewalls which delineate the abrupt edges of the ion-implanted layers. The application of this method to fabricate Schottky barrier FET's and bipolar transistors yields devices with reduced parasitic resistance without adversely impacting other related electrical parameters such as breakdown voltage and capacitance.

Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors

Metal-insulator-semiconductor structures characterized by reduced junction capacitance and methods of fabrication are disclosed. A substantially intrinsic region beneath the junction is formed by implanting selected ions. The ion implantation does not produce lateral diffusion of conventionally formed junctions, and therefore breakdown and packing density are not changed. The substantially intrinsic region does, however, increase the space charge region of the adjacent junction, thus reducing the effective capacitance. In the preferred method of fabrication, ions are implanted using the same mask employed in forming the p-n junction.

W Gosney

Papers

Metal-insulator-semiconductor structures having reduced junction capacitance and method of fabrication