scispace - formally typeset
Patent

Metal-insulator-semiconductor structures having reduced junction capacitance and method of fabrication

Reads0
Chats0
TLDR
In this paper, a substantially intrinsic region was formed by implanting selected ions, which increased the space charge region of the adjacent junction, thus reducing the effective capacitance of metal-insulator-semiconductor structures.
Abstract
Metal-insulator-semiconductor structures characterized by reduced junction capacitance and methods of fabrication are disclosed. A substantially intrinsic region beneath the junction is formed by implanting selected ions. The ion implantation does not produce lateral diffusion of conventionally formed junctions, and therefore breakdown and packing density are not changed. The substantially intrinsic region does, however, increase the space charge region of the adjacent junction, thus reducing the effective capacitance. In the preferred method of fabrication, ions are implanted using the same mask employed in forming the p-n junction.

read more

Citations
More filters
Patent

Method and apparatus for phase shifting an optical beam in an optical device

TL;DR: In this paper, an apparatus and method for high speed phase modulation of optical beam with reduced optical loss is presented. But the method is based on a first contact and is coupled to the optical waveguide at a first location in the first region outside an optical path of an optical beam to be directed through the optical beam.
Patent

Method of eliminating lattice defects in a semiconductor device

TL;DR: In this paper, conductivity-determining ions like antimony or arsenic are implanted into phosphorus-doped zones of a semi-conductor device and annealed in an inert gas atmosphere at approximately 1000° C.
Patent

Bias voltage generation circuit of ecl level for decreasing power consumption thereof

TL;DR: In this article, a bias voltage generation circuit consisting of a bias control node, a first switching unit, and a second switching unit was proposed to reduce the power consumption of the bias voltage generator during the standby period.
Patent

Method of patterning polysilicon

TL;DR: In this article, a semiconductor substrate is coated with an insulating film followed by a layer of polysilicon, which is then oxidized to convert exposed regions to silicon oxide and add further thickness to the converted oxide regions.
Patent

Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors

TL;DR: In this article, a lift-off technique was used to make ion-stopping masks with near-vertical sidewalls which delineate the abrupt edges of the ion-implanted layers.
References
More filters
Patent

Semiconductor isolation structure and method of producing

TL;DR: In this article, a monocrystalline semiconductor body is provided with a subsurface insulating layer, which is produced by bombarding the body with ions such as nitrogen, oxygen and carbon, for a time sufficient to produce a dense layer of embedded ions and at an energy level sufficient to result in ion penetration to the desired sub-surface depth.
Patent

Metal shielding for ion implanted semiconductor device

TL;DR: In this article, the use of METAL MASK against Ion BOMBARDMENT in the formation of SEMICONDUCTOR DEVICES is described. But it is not discussed in detail.
Patent

Method of manufacturing semiconductor devices

TL;DR: In this paper, a method of fabricating a TRANSISTOR HAVING EMITTER, base and collection or region is discussed, and the body part of a transistor is sent to a base to remove damage.