This paper first summarizes the complete range of analog defects and resultant faults. A complete set of metrics is then derived for measuring the quality of analog tests. The probability-based equations for fault coverage, defect level, yield coverage, and yield loss are self-consistent, and consistent with existing equations for digital test metrics. We introduce the concept of partial coverage, show that it is inherent to analog testing, and show that coverage cannot be calculated without knowing the performance specifications for a circuit, as well as the process parameter distributions. Practical methods for calculating probabilities are discussed, and simple, illustrative examples given.

Test metrics for analog parametric faults

In this paper, we propose a unified approach to partitioning, floorplanning, and retiming for effective and efficient performance optimization. The integration enables the partitioner to exploit more realistic geometric delay model provided by the underlying floorplan. Simultaneous consideration of partitioning and retiming under the geometric delay model enables us to hide global interconnect latency effectively by repositioning FF along long wires. Under the proposed geometric embedding based performance driven partitioning problem, our GEO algorithm performs multi-level top-down partitioning while determining the location of the partitions. We adopt the concept of sequential arrival time [14] and develop sequential required time in our retiming based timing analysis engine. GEO performs cluster-move based iterative improvement on top of multi-level cluster hierarchy [4], where the gain function obtained from the timing analysis is based on the minimization of cutsize, wirelength, and sequential slack. In our comparison to (i) state-of-the-art partitioner hMetis [9] followed by retiming [11] and simulated annealing based slicing floorplanning [15], and (ii) state-of-the-art simultaneous partitioning with retiming HPM [7] followed by floorplanning [15], GEO obtains 35% and 23% better delay results while maintaining comparable cutsize, wirelength, and runtime results.

/pdf/physical-planning-with-retiming-2oefjll30p.pdf

Physical planning with retiming

We propose a new Simulation-After-Test (SAT) methodology for accurate diagnosis of circuit parameters in large analog circuits. Our methodology is based on constructing a non-linear regression model using prior circuit simulation, which relates a set of measurements to the circuit's internal parameters. First, we give algorithms to select measurements that give all the diagnostic information about the Circuit-Under-Test (CUT). From these selected measurements, we solve for the internal parameters of the circuit using iterative numerical techniques. The methodology has been applied to several mixed-signal test benchmark circuits and has applications in process debugging for mixed-signal integrated circuits (ICs) as well troubleshooting and repair of board level systems.

/pdf/parametric-fault-diagnosis-for-analog-systems-using-59f7lykt3k.pdf

Parametric fault diagnosis for analog systems using functional mapping

Automatic test-pattern generation (ATPG) algorithms for analog circuits have been under intense investigation for the last several years As system design aggressively moves to system-on-a-chip (SoC) and core-based integration, hierarchical analog ATPG emerges as an even more difficult challenge Attempts to develop an effective algorithm have had varying degrees of success This article reviews some fundamental issues and recent work in hierarchical analog ATPG and presents an algorithm based on controllability and observability computation This algorithm has been implemented in a prototype tool, and results based on several case studies show the application of the technique

Hierarchical ATPG for analog circuits and systems

The problem of testing analog components continues to be the bottleneck in reducing the time-to-market of mixed-signal ICs. In this paper, we present a test generation algorithm for implicit functional testing of linear analog circuits using transient response sampling. Each specification of the circuit under test (CUT) imposes bounds on individual parametric deviations under the single fault assumption. These bounds are mapped on to "acceptable" ranges of measurements of the transient response of the CUT at various sample points using time domain sensitivity calculations. Any circuit that "passes" the applied test is also guaranteed to meet its specifications. The simplicity of the test waveform, reduced test generation time and test time show that this testing method is a good alternative to existing testing schemes.

/pdf/test-generation-for-comprehensive-testing-of-linear-analog-2w6as70ard.pdf

Test generation for comprehensive testing of linear analog circuits using transient response sampling

In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.

W. Kao

Papers

Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis