The invention provides improved methods and apparatus for control using field and control devices that provide a virtual machine environment and that communicate via an IP network. By way of non-limiting example, such field device can be an “intelligent” transmitter or actuator that includes a low power processor, along with a random access memory, a read-only memory, FlashRAM, and a sensor interface. The processor can execute a real-time operating system, as well as a Java virtual machine (JVM). Java byte code executes in the JVM to configure the field device to perform typical process control functions, e.g., for proportional integral derivative (PID) control and signal conditioning. Control networks can include a plurality of such field and control devices interconnected by an IP network, such as an Ethernet.

Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an ip network

Methods and apparatus for control configuration with versioning, security, composite blocks, edit selection, object swapping, formulaic values and other aspects

Connection objects or other such data structures facilitate establishing and configuring connections between objects that model components in a process control system. A first set of data structures (e.g. the object connection type structures) identify valid types for component-to-component pairings and the respective roles of each component in the pairing (e.g., parent or child, source or sink). A second set of data structures (e.g., the parameter connection type structures) supply similar information for parameter-to-parameter connections. Together, these data structures can be used, for example, to validate component-to-component connections suggested by the user and to automatically configure parameter-to-parameter connections. Actual connections, both at the component or parameter level, are reflected using parameter overrides within the parameterized object model—with which the connection objects are constructed.

Process control configuration system with connection validation and configuration

The invention provides improved apparatus for configuring process, environmental, industrial and other control systems. Such apparatus employs “appearance” objects (or other data and/or programming constructs) defining the appearance of configurable system components in graphical editors or other views in which the components may be depicted. “Placeholder” objects (or other constructs) persist the location, size, color, or other aspects of appearance defined by an appearance object for a configurable component in views in which it is actually depicted. By way of example, a process control configuration apparatus according to this aspect of the invention uses “configurable” objects to define blocks, loops and other components of a process control system. Appearance objects provide (or reference) icons or representations indicating how the configurable objects are to be depicted, e.g., in a configuration editor. Placeholder objects are created for each configurable object that is placed in a configuration using that editor. The placeholder objects identify the sizes, locations, colors, etc., of the icons used in the editor to represent the configurable objects.

Methods and apparatus for controlling object appearance in a process control configuration system

A system for process control comprises a server digital data processor and a client digital data processor that are coupled by a network, such as the Internet or an Intranet. The server digital data processor, which is additionally coupled to a control/sensing device and any associated interface equipment (collectively, referred to as “process control apparatus”), includes a command processor that transfers information between the network and the process control apparatus. The client digital data processor includes an information client (e.g., a so-called Internet web browser) capable of requesting and receiving an applet from the server digital data processor. The information client, further, defines a hardware-independent and operating system-independent virtual machine environment within the client digital data processor. The client digital data processor executes, within that virtual machine environment, an applet for configuring the client digital data processor as a “process controller” that establishes communications over the network with the command processor and that monitors and/or controls the process control apparatus via those communications.

Methods and apparatus for remote process control

A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Method and apparatus for testing and debugging a tightly coupled mirrored processing system

A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.

Method and apparatus for concurrency of bus operations

A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.

Walter G. Fry

Papers

Method and apparatus for testing and debugging a tightly coupled mirrored processing system

Method and apparatus for concurrency of bus operations

Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller

Method and apparatus for operating tightly coupled mirrored processors

Method and apparatus for non-snoop window reduction