Patent
Method and apparatus for concurrency of bus operations
Jeff W. Wolford,Walter G. Fry +1 more
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TLDR
In this paper, the authors propose a method and apparatus for concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency.Abstract:
A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.read more
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References
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Patent
Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
TL;DR: In this article, an arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master, which is responsive to high priority bus activities such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity.
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Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
TL;DR: In this paper, a bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master is proposed.
Patent
Access control method for multiprocessor systems
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System for fast selection of non-cacheable address ranges using programmed array logic
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Apparatus and method for a synchronous, high speed, packet-switched bus
Pradeep Sindhu,Bjorn Liencres,Jorge Cruz-Rios,Douglas Lee,Jung-Herng Chang,Jean-Marc Frailong +5 more
TL;DR: In this paper, a high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller is presented, where an arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller.