Real-time sound rendering applications are memory-intensive and computation-intensive. To speed up computation and extend the simulated area, a real-time sound rendering system based on the hardware-oriented finite difference time domain algorithm (HO-FDTD) and time-sharing architecture is proposed and implemented by the field programmable gate array (FPGA) in this study. Compared with the traditional rendering system with parallel architecture, the proposed system extends by about 37 times in the simulated area because data are stored in the on-chip block memories instead of the D flip-flops. The hardware system becomes stable after 400 time steps in the impulse response. To render a three-minute Beethoven classical music clip, the hardware system carries it out in real-time while the software simulation takes about 63 min in a computer with 4 GB RAM and an AMD Phenom 9500 Quad-core processor running on 2.2 GHz.

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A real-time sound rendering system based on the finite-difference time-domain algorithm

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 m partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary- scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 10 11 rad(Si)/s and a neutron fluence immunity of 1 10 14 n/cm 2 .

https://iopscience.iop.org/article/10.1088/1674-4926/32/7/075012/pdf

A radiation-hardened SOI-based FPGA

Despite the growing popularity of field-programmable gate arrays (FPGA), this technology still suffers from drawbacks such as larger area, higher power consumption and longer runtime than application-specific integrated circuits (ASIC). Reconfiguration capability gives FPGAs an advantage over ASIC and can make it a more appropriate option for implementing some applications. One important issue regarding the reconfiguration process is the time it takes to carry out this procedure. This paper seeks to accelerate the reconfiguration process by using a bitstream compression method with a primary focus on FPGA architecture. Since multiplexers are among the main components of FPGAs, the proposed method is focused on encoding and compression of configuration bitstream for such resources. In addition, the bitstream format and the decompression operation are designed to obtain desirable results in terms of area overhead and time improvement. Results of experiments show that in comparison to the basic scheme, the proposed design improves the reconfiguration time by 33%.

Reducing Reconfiguration Time in FPGAs

The paradigm of Internet-of-things (IoT) systems is changing from a cloud-based system to an edge-based system. These changes were able to solve the delay caused by the rapid concentration of data in the communication network, the delay caused by the lack of server computing capacity, and the security issues that occur in the data communication process. However, edge-based IoT systems performance was insufficient to process large numbers of data due to limited power supply, fixed hardware functions, and limited hardware resources. To improve their performance, application-specific hardware can be installed in edge devices, but performance cannot be improved except for specific applications due to a fixed function of an application-specific hardware. This paper introduces an edge-centric metamorphic IoT (mIoT) platform that can use various hardware modules through on-demand partial reconfiguration, despite the limited hardware resources of edge devices. In addition, this paper introduces an RISC-V based metamorphic IoT processor (mIoTP) with reconfigurable peripheral modules. We experimented to prove that the proposed structure can reduce the server access of edges and can be applied to a large-scale IoT system. Experiments were conducted in a single-edge environment and a large-scale environment combining one physical edge and 99 virtual edges. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration prediction algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to our previous study in which the prediction process was executed at the server. Furthermore, we confirmed that there is no additional reconfiguration time overhead even for the large IoT systems.

https://www.mdpi.com/2079-9292/10/17/2088/pdf

An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications

A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources We also develop a new carry chain structure with an optimized critical path Finally a newly designed configurable scan-chain is inserted The circuit is fabricated in 013 μm 1P8M 12/25/33 V logic CMOS process The test results show a correct function of 4/5-input LUT and scan-chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 725% Our results also show that the logic utilization of this work is better than that of a Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex II/Virtex 4 FPGA when implemented using only 5-LUT

https://iopscience.iop.org/article/10.1088/1674-4926/33/7/075009/pdf

A new FPGA with 4/5-input LUT and optimized carry chain

In this paper, fast configuration architecture of FPGA suitable for bitstream compression is proposed and implemented for FDP2009-II-SOPC (FDP2009-II-SOPC: Fudan Programmable device 2009-II-SOPC) FPGA with SMIC 0.13 CMOS process. This circuit features an addressable configuration register and the internal frame decoder that makes a 32-bit memory cell of FPGA addressable. The improved configuration circuit which can configuration every 32bit memory cells could provide faster configuration speed and more flexible partial configuration operations. The die size of FDP2009-II-SOPC is about 6.3mm*4.5mm=28.35mm2 and the area of this configuration circuit is about 1.7mm2. The post layout simulation shows that this fast configuration circuit of FDP2009-II-SOPC FPGA could work correctly and efficiently and the configuration time is less than 53% of that of Xilinx VirtexII series FPGA1.

Fast configuration architecture of FPGA suitable for bitstream compression

A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18 μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 × 30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.

Circuit design of a novel FPGA chip FDP2008

A novel Fudan programmable logic chip (FDP) was designed and implemented with a SMIC 0.18μm CMOS logic process.The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT.The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly.The FDP contains 1,600 programmable logic cells,160 programmable I/O,and 16kbit dual port block RAM.Its die size is 6.104mm×6.620mm,with the package of QFP208.The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.

Design and Implementation of an FDP Chip

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

https://iopscience.iop.org/article/10.1088/1674-4926/32/5/055012/pdf

A new FPGA architecture suitable for DSP applications

This paper proposes the design and implementation of a System on Programmable Chip(SoPC) interface to solve the problems of timing control and bit stream downloading of embedded Field Programmable Gate Array(FPGA) IP core in the evolvable SoPCThe FPGA interface uses asynchronous FIFO and dual port RAM structure,scalable read/write command transmission to achieve asynchronous communication between FPGA IP core and the systemEmbedded CPU achieves the on-chip bit stream configuration of FPGA IP core via FPGA interfaceHardware random number generator in the FPGA interface is used to accelerate the evolutionary algorithmAutomatic verification platform and FPGA prototyping platform are used for the verification of FPGA interface to achieve convergence of verificationTest results show that FPGA interface implements the communication between embedded CPU and FPGA IP core successfully,completes on-chip evolution

Wang Jian

Papers

Fast configuration architecture of FPGA suitable for bitstream compression

Circuit design of a novel FPGA chip FDP2008

Design and Implementation of an FDP Chip

A new FPGA architecture suitable for DSP applications

Design and Implementation of FPGA Interface for Evolvable Chip