In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.

/pdf/efficient-hardware-implementations-of-low-bit-depth-motion-58jy8bhd6q.pdf

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

Variable block-size motion estimation (VBSME) has become an important technique in H.264/AVC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/AVC based on a full-search motion estimation algorithm. A new scan order is introduced to re-use the sum of absolute differences (SAD) values of smaller sub-blocks on an "as-early-as-possible" basis, thus the complexity of the required hardware resources, such as registers, multiplexers, and controls is reduced. It also spreads the timing for the final SAD outputs so that the number of output buses is reduced. The architecture is flexible and scalable with regard to the size of the searching windows and PE arrays. Compared to the conventional approaches, the architecture shows higher throughput rate with less hardware. After logic synthesis using DongbuAnam 0.18 mum standard cell library, the number of gates is 39K (16 PEs) in two-input equivalent NAND gates and the maximum operating clock frequency is 416 MHz (256 fps@CIF).

A novel VLSI architecture for full-search variable block-size motion estimation

This paper presents a high-throughput, cost-effective implementation of six different integer transforms in the H.264/AVC high-profile coders, i.e., 4 × 4 forward, 4 × 4 inverse, forward Hadamard, inverse Hadamard, 8 × 8 forward, and 8 × 8 inverse transform, all integrated as a shared hardware. The 4 × 4 transform matrices are regularized by using permutation, partitioned into 2 × 2 blocks, and factored for maximal hardware sharing. By using two types of 4 × 4 transform matrices included in an 8 × 8 transform matrix, two different 8 × 8 transforms are both described as three steps and unified with minor modification. To improve throughput of the transform, two independent 4 × 4 transform blocks within the 8 × 8 transform block operate in parallel in the 4 × 4 transform mode, while the two-stage pipelined architecture is used in the 8 × 8 transform mode. Using 0.18-?m CMOS technology, the maximum operating frequency of the proposed multitransform architecture is 200 MHz, which achieves 4.1 Gpixels/sec throughput rate with the hardware cost of 63618 gates. Compared with existing designs, the proposed design delivers at least 54% higher throughput at 38% higher throughput/area ratio in Adaptive Block-size Transform (ABT) mode.

A Multitransform Architecture for H.264/AVC High-Profile Coders

Motion estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose high performance systolic hardware architectures for 1BT based fixed block size (FBS) and variable block size (VBS) ME. The proposed ME hardware architectures perform full search ME for 4 Macroblocks in parallel and they are faster than the 1BT based ME hardware reported in the literature. They use less on-chip memory than the previous 1BT based ME hardware by using a novel data reuse scheme and memory organization. The proposed VBS ME hardware is the first 1BT based ME hardware implementing VBS ME. The proposed hardware architectures are implemented in Verilog HDL. The FBS ME and VBS ME hardware consume %34 and %49 of the slices in a Xilinx XC2VP30-7 FPGA, respectively. They can work at 113 MHz in the same FPGA and are capable of processing 49 1920times1080 full High Definition frames per second. Therefore, they can be used in consumer electronics products that require real-time video processing or compression.

/pdf/high-performance-hardware-architectures-for-one-bit-5a7pfkomi2.pdf

High performance hardware architectures for one bit transform based motion estimation

To achieve superior performance, rate-distortion optimized motion estimation (ME) for variable block size (RDO VBSME) is often used in state-of-the-art video coding systems such as the H.264 JM software. However, the complexity of RDO-VBSME is very high both for software and hardware implementations. In this paper, we propose a hardware-friendly ME algorithm called RDOMFS with a novel hardware-friendly rate-distortion (RD)-like cost function, and a hardware-friendly modified motion vector predictor. Simulation results suggest that the proposed RDOMFS can achieve essentially the same RD performance as RDO-VBSME in JM. We also propose a matching hardware architecture with a novel Smart Snake Scanning order which can achieve very high data re-use ratio and data throughout. It is also reconfigurable because it can achieve variable data re-use ratio and can process variable frame size. The design is implemented with TSMC 0.18 μm CMOS technology and costs 103 k gates. At a clock frequency of 63 MHz, the architecture achieves real-time 1920 × 1080 RDO-VBSME at 30 frames/s. At a maximum clock frequency of 250 MHz, it can process 4096 × 2160 at 30 frames/s.

Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture

VBSME (variable block size motion estimation) is adopted in the MPEG-4 AVC/H.264 standard. In order to increase the hardware utilization for VBSME with FSBMA (full search block matching algorithm), this paper proposed a new high-performance reconfigurable VLSI architecture to support "meander"-like scan format for a high data reuse of search area. The architecture can support the three data flows of the scan format through a reconfigurable computing array and a memory of the search area. The computing array can achieve 100% processing element (PE) utilization and can reuse the smaller blocks' SADs to calculate 41 motion vectors (MVs) of a 16X16 block in parallel. The design is implemented with TSMC 0.18 mum CMOS technology. Under a clock frequency of 180 MHz, the architecture allows the real-time processing of 1280 x 720 at 45 fps in a search range [-16, +16].

A high-performance reconfigurable VLSI architecture for vbsme in H.264

This paper presents a configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip. This circuit could write configuration data into FDP and read back data from FDP successfully. Comparing with Xilinx Virtex Series FPGA chips, the smallest configuration section of which is one data-frame, the proposed circuit could write each single memory cell in FDP, providing more flexible configuration operations. A standard configuration interface, Serial Peripheral Interface (SPI), is added in this circuit to replace using the expensive Xilinx Platform configuration Flash PROMs. A group of high precise sensitive amplifiers is adopted in this configuration circuit, which are used to magnify the read back data values. Through a novel write/read asynchronous FIFO structure in FDP, which divides the external interface and internal configuration circuit into two clock domains, designers could set the external clock and internal clock separately. Basic functions of the configuration circuit have been correctly verified by Altera DE2 development board platform. The post layout simulation results indicate via this configuration circuit, each data frame in FDP could be written in 4 mus, and could be read back in 5 mus. The total configuration time of FDP chip is about 6.5 ms.

Design and implementation of the configuration circuit for FDP FPGA

This paper presents three new types of pulse quenching mechanism (NMOS-to-PMOS, PMOS-to-NMOS and NMOS-to-NMOS) and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are: (1) with the exception of PMOS-to-PMOS, pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process. (2) Pulse quenching in general correlates weakly with ion LET, but strongly with incident angle and layout style (i.e. spacing between transistors and n-well contact area). (3) Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

Effect of charge sharing on the single event transient response of CMOS logic gates

The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2-D architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 um CMOS technology. The proposed design is more efficient than the existing typical designs. Under a clock frequency of 100 Mhz, the architecture allows the real-time processing of 4096times2048 at 60 fps.

A high-performance reconfigurable 2-D transform architecture for H.264

We present an iterative algorithm to compute the response of an RF circuit in which the MOSFET is modeled by a system of partial differential-algebraic equations, rather than an equivalent circuit. The problem amounts to the solution of a nonlinear PDE coupled to a linear ODE. We illustrate the algorithm with the simulation of the Colpitts oscillator.

http://ieeexplore.ieee.org/iel5/7722/21171/00982650.pdf

Lai Jinmei

Papers

A high-performance reconfigurable VLSI architecture for vbsme in H.264

Design and implementation of the configuration circuit for FDP FPGA

Effect of charge sharing on the single event transient response of CMOS logic gates

A high-performance reconfigurable 2-D transform architecture for H.264

Simulation of RF circuits with a PDE model of the MOSFET