The invention provides a ring first in first out buffer (FIFO) and a data transmission interface, a system, a method, a synchronization circuit synchronizes a comparison result of a write pointer anda read pointer by a specific number of clock signal cycles, It can realize the data transmission between different clock domains, and can increase the Jitter margin of the ring FIFO buffer and improvethe anti-noise ability of the ring FIFO buffer when the FIFO depth is the same Further, the synchronization circuit synchronizes the comparison result of the write pointer and the read pointer by (M/2 - 0 5) clock signal cycles, so that the ring FIFO buffer has a Jitter margin of (M/2-1 5) clock signal cycles when it is read empty and full, where M is the depth of the FIFO When the FIFO depthis 4, the invention is suitable for the application of DDR, and can obtain Jitter margin of 05 clock signal cycles both empty and full under minimum hardware resource consumption

Ring FIFO buffer and data transmission interface, system and method

The invention provides a data processing method. The data processing method comprises the steps as follows: storing received data grouping when detecting that a packet tail indication port is an ineffective signal and a packet discarding port is an ineffective signal; storing received data grouping when detecting that the packet tail indication port is an effective signal and the packet discardingport is an ineffective signal; adding 1 to the number of data packets and setting an empty packet indication port as an ineffective output signal; discharging received data grouping when detecting that the packet tail indication port is an ineffective signal and the packet discarding port is an effective signal; discharging received data grouping when detecting that the packet tail indication port is an effective signal and the packet discarding port is an effective signal by a control unit; controlling a writing address to offset to the packet head position of a data packet where the data grouping belongs to by a writing address control unit. The invention also provides a data processing device. By means of the method, caching with data packets as basic units can be realized, and packetloss processing can be realized as required.

Data processing method and device, computer storage medium and FIFO (first input first output) equipment

Provided are a multi-digit cross-clock domain processing method and apparatus. The method comprises: acquiring data output from a sending clock domain side to a receiving clock domain side, wherein a sending clock domain and a receiving clock domain are different clock domains (S102); detecting whether the data changes (S104); and if the data changes, updating the data and then outputting same, and if the data does not change, keeping the original output data (S106).

Multi-digit data cross-clock domain processing method and apparatus

The invention discloses a low-power consumption method based on a program storage address main bus system. The program storage address main bus system comprises a program memory, a microprocessor andan address main bus, wherein the microprocessor is used for sending address information to the program memory through the address main bus so as to enable the program memory to send program data according to the corresponding addresses. The method comprises the following steps: transcoding binary address directories of programs stored in a software layer into address directories having gray code formats by utilizing the software layer of the program memory; receiving the address information, sent by the microprocessor, having the gray code formats through the address main bus by utilizing theprogram memory; and searching the corresponding program data to the microprocessor according to the address directories having the gray code formats. According to the low-power consumption method disclosed by the invention, power consumption caused by turning address main bus signals of the program storage is reduced to a greatest extent in a minimum hardware overhead form.

Low-power consumption method based on program storage address main bus system

A FIFO circuit for a DDR memory system includes a pointer generator and a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.

FIFO circuit applied to DDR memory system

The invention discloses asynchronous FIFO across clock domains, and relates to the technical field of integrated circuit design. The FIFO includes a BRAM array and an FIFO controller, a writing address latch, a writing data latch, a reading address latch and a reading data latch connected with the BRAM array. A binary-to-Gray-code converter is disposed between a reading adder and a first comparator. A binary-to-Gray-code converter is disposed between a reading counter and a first reference point. A binary-to-Gray-code converter is disposed between a writing counter and a second reference point. A binary-to-Gray-code converter is disposed between a writing adder and a third comparator. According to the FIFO, an area occupied by FIFO control logic can be reduced, burrs of internal signals ina working process can be reduced, and the stability of the FIFO in working can be improved.

Asynchronous FIFO across clock domains and data processing method

The invention discloses an ALU circuit in an FPGA and relates to the field of integrated circuit design. The ALU circuit comprises M addition units and a carry lookahead adder, wherein M is an integergreater than or equal to 8; each addition unit comprises a three-input full adder, a first selector, a second selector and a third selector, and output of the second selector and output of the thirdselector of each addition unit are used as output of the corresponding addition unit; each three-input full adder is provided with three input ends and two output ends, namely a sum value data outputend and a carry data output end; a sum value output end of the carry lookahead adder is connected with a first input end of a fourth selector and also connected with a second input end of the fourth selector through an inverter, and an output end of the fourth selector serves as a third output end of the ALU circuit; and the carry lookahead adder is also provided with a first output end used for outputting first carry data and a second output end used for outputting second carry data. Through the ALU circuit, a high-efficiency small-area DSP module is realized.

Wang Zhichao

Papers

Asynchronous FIFO across clock domains and data processing method

ALU circuit in FPGA