The invention discloses an ALU circuit in an FPGA and relates to the field of integrated circuit design. The ALU circuit comprises M addition units and a carry lookahead adder, wherein M is an integergreater than or equal to 8; each addition unit comprises a three-input full adder, a first selector, a second selector and a third selector, and output of the second selector and output of the thirdselector of each addition unit are used as output of the corresponding addition unit; each three-input full adder is provided with three input ends and two output ends, namely a sum value data outputend and a carry data output end; a sum value output end of the carry lookahead adder is connected with a first input end of a fourth selector and also connected with a second input end of the fourth selector through an inverter, and an output end of the fourth selector serves as a third output end of the ALU circuit; and the carry lookahead adder is also provided with a first output end used for outputting first carry data and a second output end used for outputting second carry data. Through the ALU circuit, a high-efficiency small-area DSP module is realized.

Xiong Xuanlin

Papers

ALU circuit in FPGA