A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

High-voltage vertical transistor with a multi-gradient drain doping profile

A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

High-voltage transistor with buried conduction layer

A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor. The invention also includes conductive polysilicon lines and thin film transistors.

Thin film transistors

In accordance with the present invention, a switching converter includes two transistors Q 1 and Q 2 parallel-connected between two terminals. Transistor Q 1 is optimized to reduce the dynamic loss and transistor Q 2 is optimized to reduce the conduction loss. Q 1 and Q 2 are configured and operated such that the dynamic loss of the converter is dictated substantially by Q 1 and the conduction loss of the converter is dictated substantially by Q 2 . Thus, the tradeoff between these two types of losses present in conventional techniques is eliminated, allowing the dynamic and conduction losses to be independently reduced. Further, the particular configuration and manner of operation of Q 1 and Q 2 enable reduction of the gate capacitance switching loss when operating under low load current conditions.

Method and circuit for reducing losses in DC-DC converters

[A circuit to discharge a capacitance between input terminals of a power system is disclosed. An example circuit includes a control circuit coupled to an input of a power system. The control circuit is coupled to detect whether an electrical energy source is coupled to an input of the power system. A switch is also included and is coupled to the control circuit and to the input of the power system. The control circuit is coupled to drive the switch in a first operating mode when the electrical energy source is coupled to the input of the power system. The control circuit is coupled to drive the switch in a second operating mode when the electrical energy source is uncoupled from the input of the power system. A capacitance coupled between input terminals of the input of the power system is discharged through the switch to a threshold voltage in less than a maximum period of time from when the electrical power source is uncoupled from the input terminals of the power system.

Method and apparatus for implementing a power converter input terminal voltage discharge circuit

A bi-directional switch includes a well region of a first conductivity type placed within a substrate. A first region of second conductivity type is placed within the well. A second contact region of second conductivity type is placed within the well. A drift region of second conductivity is placed between the first contact and the second contact. The drift region is separated from the first contact by a first channel region and is separated from the second contact by a second channel region. A first gate region is placed over the first channel region and a second gate region over the second channel region.

Bi-directional MOSFET switch.

In a method for constructing a semiconducting device, within a substrate of a first conductivity type there is formed a well of second conductivity type. Within the well, an extended drain region of a first conductivity type is formed. An insulating region over the extended drain region is formed. A gate region is formed on a surface of the substrate. A first side of the gate region is adjacent to a first end of the extended drain region. A drain region of the first conductivity type is formed. The drain region is in contact with a second end of the extended drain region. A source region is formed on a second side of the gate region.

Wayne Bryan Grabowski

Papers

Bi-directional MOSFET switch.

Method of making high voltage transistor

High voltage transistor