For fully autonomous implantable or body-worn devices running on harvested energy, the peak and average power dissipation of the radio transmitter must be minimized. Additionally, link symmetry must be maintained for peer-to-peer network applications. We propose a highly integrated 90 μW 400 MHz MICS band transmitter with an output power of 20 μW, leading to a 22% global efficiency - the highest reported to date for low-power MICS band systems. We introduce a new transmitter architecture based on cascaded multi-phase injection locking and frequency multiplication to enable low power operation and high global efficiency. Our architecture eliminates slow phase/delay-locked loops for frequency synthesis and uses injection locking to achieve a settling time <;250 ns permitting very aggressive duty cycling of the transmitter to conserve energy. At a data-rate of 200 kbps, the transmitter achieves an energy efficiency of 450 pJ/bit. Our 400 MHz local oscillator topology demonstrates a figure-of-merit of 204 dB while locked to a stable crystal reference. The transmitter occupies 0.04 mm2 of active die area in 130 nm CMOS and is fully integrated except for the crystal and the matching network.

A Sub-100 $\mu$ W MICS/ISM Band Transmitter Based on Injection-Locking and Frequency Multiplication

This paper presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratio of the frequency divider. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process, thereby reducing the settling time. To further enhance the locking speed, an auxiliary charge pump is employed to supply currents to the loop filter during the fast-locking mode to facilitate a rapid frequency acquisition. The proposed technique is incorporated in the design of a 5-GHz PLL. Fabricated in the TSMC 0.18-μm CMOS technology, the whole PLL dissipates 11 mA from a 1.8-V supply. The measured settling time is considerably improved over previous bandwidth-switching method. At 5.34 GHz, the phase noise measured at 1-MHz offset is -114.3 dBc/Hz, and the reference spurs at 10-MHz offset are lower than -70 dBc.

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915 MHz OOK/FSK PLL-based wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54 dB gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5 μV and a CMRR of 75 dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters. The 915 MHz FSK/OOK transmitter offers data rates up to 1.5 Mbps and a maximum output power of 0 dBm. The 4×3 mm2 chip fabricated in a 0.13 μm CMOS process dissipates 5.03 mW from a 1.2 V supply. Experimental measurements characterize the electrical performance of the wireless SoC. In vivo measurement results from freely moving rats are also presented.

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915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters

In this paper, we present four examples of highly integrated 60 GHz single-chip CMOS 90 nm digital radios and phased array solutions. These solutions include for the first time digital-to-analog/analog-to-digital conversion and embedded multi-gigabit mixed signal modem requiring no external processing. This convergence of 60 GHz CMOS digital radio, low power multi-gigabit mixed-signal processing and digital signal processing on a single chip offers the lowest energy per bit transmitted wirelessly at multi-gigabit rate to meet the very stringent low-power specifications for battery operated consumer electronic portable devices. Layout and temperature dependent 60 GHz CMOS 90 nm model development and critical high performance analog and mixed building blocks are presented as fundamental enablers for single chip integration. The designs have been optimized for robustness against process variation and temperature, and verified by measurement results.

60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching or loop tilter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer- N PLL's): a signal-tonoise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.

/pdf/an-adaptive-pll-tuning-system-architecture-combining-high-3z5j1e5zcy.pdf

An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time

A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal. The variable frequency divider determines a value of the variable divisor in accordance with the digital output to reduce the phase difference between the divided feedback signal and the reference signal .

Phase locked loop capable of fast locking

This paper presents a synchronous 50% duty-cycle clock generator (DCCG). The proposed DCCG circuit comprises of a clock generator and a phase error integrator. The clock generator is edge-triggered by an input signal to produce an output whose pulse width is determined by a delay line. The delay line is controlled by the phase error integrator which detects the phase difference between the input and output signals. The proposed DCCG is designed such that when the phase error is zeroed, i.e., the input and output signals are synchronized, the delay is properly adjusted and the output signal duty cycle converges to 50%. The proposed DCCG is implemented in a 0.35-μm CMOS process. The circuit can operate from 70 to 500 MHz, and accommodates a wide range of input duty cycle ranging from 5% to 95%. The duty-cycle error of the output signal is less than 1.5%. Operated from a 3.3-V supply voltage, this circuit dissipates 7 mA at 500 MHz.

A Synchronous 50% Duty-Cycle Clock Generator in 0.35- $\mu$ m CMOS

A multi-band FSK transmitter (Tx) is presented in this paper. The Tx is designed to operate at the ISM frequency bands at 433/868/915 MHz, 2.4 GHz, and MICS band at 402~405 MHz, and supports a data rate well over 1 Mbps. The Tx adopts an analog modulator which allows a deviation frequency ranging from 714 kHz to 3.2 MHz. In addition, this work proposes an inductor-less wideband mixer and a voltage-controlled oscillator to save the chip area. Fabricated in a 0.18-μm CMOS process, the proposed Tx consumes 8.9 mA to 12 mA from a 1.8-V supply voltage at different frequency bands. The measured FSK errors range from 13.9 % to 15.4 %, which are adequate for most low-cost wireless applications. The proposed multi-band Tx occupies an area of 1.6 mm × 1.9 mm.

A 400-MHz/900-MHz/2.4-GHz multi-band FSK transmitter in 0.18-μm CMOS

This paper presents a 5GHz phase-locked loop (PLL) with a fast-locking capability. During frequency locking, the proposed fast-settling technique dynamically adjusts the divide ratio of the frequency divider to keep the instantaneous phase error at the PFD input small. As a result, the locking time is greatly reduced. At a loop bandwidth of 20kHz, the measured settling time is less than 10µs, which is roughly 14× faster than a traditional PLL. Fabricated in a 0.18µm CMOS process, this PLL dissipates 9.5mA from a 1.8V supply. The measured phase noise is −117.5dBc/Hz at 1MHz offset.

Wei-Hao Chiu

Papers

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

Phase locked loop capable of fast locking

A Synchronous 50% Duty-Cycle Clock Generator in 0.35- $\mu$ m CMOS

A 400-MHz/900-MHz/2.4-GHz multi-band FSK transmitter in 0.18-μm CMOS

A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18-µm CMOS