http://www.cas.mcmaster.ca/~sancheg/EE_UCU2006_thesis/biblio/Methods%20for%20Evaluating%20and%20Covering%20the%20Design%20Space%20during%20Early%20Design%20Development%20%28ucb-erl_m03-32_DSE_survey%29.pdf

Methods for evaluating and covering the design space during early design development

The fact that there are more embedded computers than general-purpose computers and that we are impacted by hundreds of them every day is no longer news. What is news is that their increasing performance requirements, complexity and capabilities demand a new approach to their design. 

Fisher, Faraboschi, and Young describe a new age of embedded computing design, in which the processor is central, making the approach radically distinct from contemporary practices of embedded systems design. They demonstrate why it is essential to take a computing-centric and system-design approach to the traditional elements of nonprogrammable components, peripherals, interconnects and buses. These elements must be unified in a system design with high-performance processor architectures, microarchitectures and compilers, and with the compilation tools, debuggers and simulators needed for application development. 

In this landmark text, the authors apply their expertise in highly interdisciplinary hardware/software development and VLIW processors to illustrate this change in embedded computing. VLIW architectures have long been a popular choice in embedded systems design, and while VLIW is a running theme throughout the book, embedded computing is the core topic. Embedded Computing examines both in a book filled with fact and opinion based on the authors many years of R&D experience.

? Complemented by a unique, professional-quality embedded tool-chain on the authors' website, http://www.vliw.org/book
? Combines technical depth with real-world experience 
? Comprehensively explains the differences between general purpose computing systems and embedded systems at the hardware, software, tools and operating system levels. 
? Uses concrete examples to explain and motivate the trade-offs.

Table of Contents

Preface
Chapter 1: An Introduction to Embedded Processing
Chapter 2: An Overview of VLIW and ILP
Chapter 3: An Overview of ISA Design
Chapter 4: Architectural Structures in ISA design 
Chapter 5: Microarchitecture Design 
Chapter 6: System Design and Simulation
Chapter 7: Embedded Compiling and Toolchains 
Chapter 8: Compiling for VLIWs and ILP 
Chapter 9: The Run-time System 
Chapter 10: Application Design and Customization 
Chapter 11: Application Areas 
Appendix A: The VEX System 
Appendix B: Glossary 
Appendix C: Bibliography

Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools

Many times we are faced with the proliferation of definitions, concepts, languages, and tools in certain (research) topics. But often there is a gap between what is provided by existing technologies and what is needed by their users. The strengths, limitations, and needs of the available technologies can be dubious. The same applies to software architectures, and specifically to languages designed to represent architectural models. Tens of different architectural languages have been introduced by the research and industrial communities in the last two decades. However, it is unclear if they fulfill the user's perceived needs in architectural description. As a way to plan for next generation languages for architectural description, this study analyzes practitioners' perceived strengths, limitations, and needs associated with existing languages for software architecture modeling in industry. We run a survey by interviewing 48 practitioners from 40 different IT companies in 15 countries. Each participant is asked to fill in a questionnaire of 51 questions. By analyzing the data collected through this study, we have concluded that 1) while practitioners are generally satisfied with the design capabilities provided by the languages they use, they are dissatisfied with the architectural language analysis features and their abilities to define extra-functional properties; 2) architectural languages used in practice mostly originate from industrial development instead of from academic research; 3) more formality and better usability are required of an architectural language.

http://www.ivanomalavolta.com/files/papers/TSE_2013.pdf

What Industry Needs from Architectural Languages: A Survey

Model checking software for microcontrollers

As more embedded systems are built using FPGA platforms, there is an increasing need to support processors in FPGAs. One option is the soft processor, a programmable instruction processor implemented in the reconfigurable logic of the FPGA. Commercial soft processors have been widely deployed, and hence we are motivated to understand their microarchitecture. We must re-evaluate microarchiteture in the soft processor context because an FPGA platform is significantly different than an ASIC platform---for example, the relative speed of memory and logic is quite different in the two platforms, as is the area cost. In this paper we present an infrastructure for rapidly generating RTL models of soft processors, as well as a methodology for measuring their area, performance, and power. Using our automatically-generated soft processors we explore the microarchitecture trade-off space including: (i) hardware vs software multiplication support; (ii) shifter implementations; and (iii) pipeline depth, organization, and forwarding. For example, we find that a 3-stage pipeline has better wall-clock-time performance than deeper pipelines, despite lower clock frequency. We also compare our designs to Altera's NiosII commercial soft processor variations and find that our automatically generated designs span the design space while remaining very competitive.

/pdf/the-microarchitecture-of-fpga-based-soft-processors-47689m6q2t.pdf

The microarchitecture of FPGA-based soft processors

Given the growth in application-specific processors, there is a strong need for a retargetable modeling framework that is capable of accurately capturing complex processor behaviors and generating efficient simulators. We propose the operation state machine (OSM) computation model to serve as the foundation of such a modeling framework. The OSM model separates the processor into two interacting layers: the operation layer where operation semantics and timing are modeled, and the hardware layer where disciplined hardware units interact. This declarative model allows for direct synthesis of micro-architecture simulators as it encapsulates precise concurrency semantics of microprocessors. We illustrate the practical benefits of this model through two case studies - the StrongARM core and the PowerPC-750 superscalar processor. The experimental results demonstrate that the OSM model has excellent modeling productivity and model efficiency. Additional applications of this modeling framework include derivation of information required by compilers and formal analysis for processor validation.

/pdf/flexible-and-formal-modeling-of-microprocessors-with-5e0rtxy7sw.pdf

Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation

Rapidly increasing design and manufacturing non-recurring engineering (NRE) costs are prompting a shift in electronic design from hardwired application specific integrated circuits (ASICs) to the use of software on programmable platforms. However, in order to minimize the power and performance overhead of such processors, we are seeing the introduction of domain or application specific processors such as network and communication processors. The design of such specialized processors requires software development tools such as simulators and compilers. In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written in Architecture Description Languages (ADLs). In this paper, we present the Mescal Architecture Description Language (MADL). MADL features a two-layer structure, a core layer and an annotation layer. The core layer is based on a formal and flexible microprocessor model -- the operation state machine (OSM), which enables MADL to express the concurrency at the operation execution level for a wide range of architectures. We address the challenges faced in designing the core layer to combine the OSM model with techniques for achieving compact processor descriptions. The annotation layer features a generic syntax that allows creating annotation schemes to specify implementation dependent or tool specific information. To show the effectiveness of MADL, we present an MADL-based simulator synthesis framework that has been used to generate efficient cycle accurate simulators and instruction set simulators with very low development effort. We also describe our annotation schemes that enable the extraction of architecture properties for use in instruction scheduling and integer-linear-programming based register allocation. Our experimental results demonstrate the efficacy of MADL as a practical and promising language for the development of programmable platforms.

A formal concurrency model based architecture description language for synthesis of software development tools

Architecture Description Languages for Retargetable Compilation.

Increasing design and manufacturing costs are prompting a shift in electronic design from hardwired application-specific integrated circuits (ASICs) to the use of software on programmable platforms In order to minimize the power and performance overhead of such platforms, domain or application-specific processors have been used The development of such processors requires not only traditional electronic design automation tools but also processor-specific software tools such as compilers and instruction set simulators In early development stages when multiple processor design points are explored, it is necessary to have the software tools synthesized from high level processor descriptions This dissertation presents an approach that aims to automate the synthesis of these software tools The foundation of the approach is a novel concurrency model, the operation state machine (OSM) The OSM model views a processor in two interacting levels: the operation level where instruction behavior is represented and the hardware level where resources required for simplifies the specification of concurrency and control semantics without compromising flexibility This dissertation then presents the MESCAL Architecture Description Language (MADL) which is designed using the OSM model It describes the major design considerations of MADL and the synthesis of software tools including cycle-accurate simulators, instruction set simulators, disassemblers, and binary decoders from MADL-based processor models It further goes on to show how this description can be used to extract reservation tables for use in instruction schedulers in compilers Experimental results show that the MADL-based approach is very effective in supporting these software tools and the synthesized cycle-accurate simulators have competitive simulation speeds compared to their hand-coded counterparts

Modeling and description of embedded processors for the development of software tools

In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation level concurrency maps to the microarchitectural level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication sub-system through a rigorous modeling approach based on a formal concurrency model, the Operation State Machine (OSM). We first introduce the basic notions and concepts of OSM and show by example how this model can be used to represent the inherent concurrency in the architecture and microarchitecture of processors. Then we demonstrate the applicability of OSM in modeling on-chip communication architectures (OCAs) by walking though a router based packet switching network example and a bus example. Due to the fact that the OSM model is naturally suited to handle the operation and microarchitecture level concurrencies of OCAs as well, our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multi-PE SoC prototypes. To demonstrate the flexibility of this methodology, we choose two distinct system configurations with different types of OCA: a 4x4 mesh network of 16 PEs, and a cluster of 4 PEs connected by a bus. We show that by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design. In addition to improving design quality, this methodology also results in significantly shortened design-time.

Wei Qin

Papers

Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation

A formal concurrency model based architecture description language for synthesis of software development tools

Architecture Description Languages for Retargetable Compilation.

Modeling and description of embedded processors for the development of software tools

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation