FPGA-based real-time epileptic seizure classification using Artificial Neural Network

Nonlinear dynamics has recently been extensively used to study epilepsy due to the complex nature of the neuronal systems. This study presents a novel method that characterizes the dynamic behavior of pediatric seizure events and introduces a systematic approach to locate the nullclines on the phase space when the governing differential equations are unknown. Nullclines represent the locus of points in the solution space where the components of the velocity vectors are zero. A simulation study over 5 benchmark nonlinear systems with well-known differential equations in three-dimensional exhibits the characterization efficiency and accuracy of the proposed approach that is solely based on the reconstructed solution trajectory. Due to their unique characteristics in the nonlinear dynamics of epilepsy, discriminative features can be extracted based on the nullclines concept. Using a limited training data (only 25% of each EEG record) in order to mimic the real-world clinical practice, the proposed approach achieves 91.15% average sensitivity and 95.16% average specificity over the benchmark CHB-MIT dataset. Together with an elegant computational efficiency, the proposed approach can, therefore, be an automatic and reliable solution for patient-specific seizure detection in long EEG recordings.

Patient-Specific Seizure Detection Using Nonlinear Dynamics and Nullclines

Closed-loop stimulation of many neurological disorders, such as epilepsy, is an emerging technology and regarded as a promising alternative for surgical and drug treatment. In this paper, a real-time seizure detection algorithm based on STFT and support vector machine (SVM) and its field-programmable gate array (FPGA) implementation are proposed. With a two-stage patient-specific channel selection and feature selection mechanism, those redundant and uncorrelated spectral features are removed from the entire feature set. The evaluation results on CHB-MIT epilepsy database show that the mean detection latency of the proposed algorithm is 6 s, the sensitivity is 98.4%, and the false detection rate is 0.356/h. The performance of our proposed algorithm is comparable to other existing seizure detection algorithms. Moreover, we implement the proposed seizure detection algorithm on Xilinx Zynq-7000 XC7Z020 with high level synthesis. Each classification of the input electroencephalography signal can be finished within 313 $\mu \text{s}$ , and the power consumption of the programmable logic is only 380 mW at 100 MHz. In hardware implementation, an optimization strategy for the nested-loop structure within nonlinear SVM is proposed to improve pipeline efficiency. Compared with existing method, the experimental result shows that our method can speed up the nonlinear SVM by $1.70\times $ , $1.53\times $ , $1.37\times $ , and $1.26\times $ with the unroll factor equal to 1–4 at the same DSP utilization rate. The evaluation results affirm the possibility of integrating the proposed algorithm and FPGA implementation into a wearable seizure control device.

Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM

Epilepsy prediction through optimized multidimensional sample entropy and Bi-LSTM

An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

Automated real time seizure detection is difficult since detection sensitivity, false detection rate and seizure onset detection latency need to be considered simultaneously. Traditional pattern recognition and classification system usually suffers huge performance variation due to patient specificity and algorithm inadaptability. To address this problem, we propose a two stage seizure detection system which integrates off-line channel selection and feature selection before the construction of the final model. This system allows patient specific channel selection and flexible feature set extraction for individual patient, so that a more compact and reliable model could be developed. Employing the two stage scheme not only decreases hardware cost in signal readout and feature extraction, but also remarkably improves detection sensitivity and reduces false detections. Mutual information based method is used for channel selection, while Random Forests and nonlinear SVM-RFE are evaluated for feature selection. The whole system achieves a mean detection latency of 6 seconds and a false detection rate of 0.356 per hour. Based on the test dataset, the sensitivity is found to 74.2% by sample or 98.4% by record with only two detection misses. Our design is also hardware-friendly, which could be implemented as a single chip closed loop neural modulation system.

Integrating channel selection and feature selection in a real time epileptic seizure detection system

A configurable long integer multiplier tailored to subthreshold operation is presented for ultra-low-power asymmetric en/decryption in semi-passive or passive systems. The multiplier is composed of radix-4 booth de/encoders and two ${544\times 16}$ -bit partial product reduction tree arrays and reconfigurable data paths. The architecture can be configured for multiple multiplications with different bit size. Novel 6–2 compressors are applied to the reduction tree with 4–2 compressors. The tree can compresses 16 bit products and carry-ins into 1 bit sum and carry within the delay of 6 XOR gates. Innovatively, a novel custom ratioed logic style is adopted in critical logic paths to fundamentally speed up the subthreshold operation. Fabricated in 65-nm CMOS, the proposed design indicates competent subthreshold operation. It can operate at 0.35-V supply with throughput of 376 Mb/s, with power consumption of 20.8 ${\mu }\text{W}$ in 1024-bit (modular) multiplication.

A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption

Sophisticated subthreshold passive radio frequency identification tag’s baseband processor (BBP) core design for ultralow-power Internet of Things end devices is presented in this paper. Custom logic cells and tailored logic architectures are applied to eliminate timing violations when the operating voltage is much lower than nominal level. For the consideration of limited availability of radio frequency power, power-aware scheme is applied to the key modules, including PIE decoding and command receiving. Furthermore, Galois linear feedback shift register and double-edge-triggered techniques help to improve clock efficiency and reduce the impact of frequency variation in data link portions. Importantly, a novel custom ratioed logic style is adopted in key modules to fundamentally speed up signals’ propagation at ultralow-voltage. The proposed BBP was fabricated in 90-nm CMOS as well as the regular design with the same function. It was also implemented in the tag chip’s fabrication. In measurement the proposed design indicates good robustness and is much more competent for subthreshold operation. It can operate below 0.3 V with power consumption below 130 nW.

A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags

For pulsed laser ranging systems, the accuracy of the time-to-digital converter (TDC) measurement directly determines the accuracy of the system's ranging. This work uses the internal carry chain of the FPGA to construct the delay chain, together with the encoder, coarse time counter, mean filtering and the trigger modules build up the proposed TDC design. In order to ensure the consistency of the delay chain, this work utilizes the entire CARRY4 carry chain as a single delay unit, and the total delay of the delay chain needs to be more than one clock cycle. Therefore, with careful verifications, 160 delay units are connected in series to form a completed delay chain. In order to reduce the complexity of the design, this work partitions the 160-bit input encoder into five 32-bit input encoders, which is equivalent to divide the delay chain into five segments and then accumulate all the statistical results. The measured results show that the TDC measurement resolution can reach 63.3ps, and the ranging accuracy of the ranging system is 0.95cm, while the measurement error is 0.38cm, and the logic complexity is 3k LUTS and 4k DFFS.

Weiwei Shi

Papers

Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM

Integrating channel selection and feature selection in a real time epileptic seizure detection system

A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption

A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags

A 63.3ps TDC Measurement System Based on FPGA for Pulsed Laser Ranging