FPGA-based real-time epileptic seizure classification using Artificial Neural Network

Nonlinear dynamics has recently been extensively used to study epilepsy due to the complex nature of the neuronal systems. This study presents a novel method that characterizes the dynamic behavior of pediatric seizure events and introduces a systematic approach to locate the nullclines on the phase space when the governing differential equations are unknown. Nullclines represent the locus of points in the solution space where the components of the velocity vectors are zero. A simulation study over 5 benchmark nonlinear systems with well-known differential equations in three-dimensional exhibits the characterization efficiency and accuracy of the proposed approach that is solely based on the reconstructed solution trajectory. Due to their unique characteristics in the nonlinear dynamics of epilepsy, discriminative features can be extracted based on the nullclines concept. Using a limited training data (only 25% of each EEG record) in order to mimic the real-world clinical practice, the proposed approach achieves 91.15% average sensitivity and 95.16% average specificity over the benchmark CHB-MIT dataset. Together with an elegant computational efficiency, the proposed approach can, therefore, be an automatic and reliable solution for patient-specific seizure detection in long EEG recordings.

Patient-Specific Seizure Detection Using Nonlinear Dynamics and Nullclines

Closed-loop stimulation of many neurological disorders, such as epilepsy, is an emerging technology and regarded as a promising alternative for surgical and drug treatment. In this paper, a real-time seizure detection algorithm based on STFT and support vector machine (SVM) and its field-programmable gate array (FPGA) implementation are proposed. With a two-stage patient-specific channel selection and feature selection mechanism, those redundant and uncorrelated spectral features are removed from the entire feature set. The evaluation results on CHB-MIT epilepsy database show that the mean detection latency of the proposed algorithm is 6 s, the sensitivity is 98.4%, and the false detection rate is 0.356/h. The performance of our proposed algorithm is comparable to other existing seizure detection algorithms. Moreover, we implement the proposed seizure detection algorithm on Xilinx Zynq-7000 XC7Z020 with high level synthesis. Each classification of the input electroencephalography signal can be finished within 313 $\mu \text{s}$ , and the power consumption of the programmable logic is only 380 mW at 100 MHz. In hardware implementation, an optimization strategy for the nested-loop structure within nonlinear SVM is proposed to improve pipeline efficiency. Compared with existing method, the experimental result shows that our method can speed up the nonlinear SVM by $1.70\times $ , $1.53\times $ , $1.37\times $ , and $1.26\times $ with the unroll factor equal to 1–4 at the same DSP utilization rate. The evaluation results affirm the possibility of integrating the proposed algorithm and FPGA implementation into a wearable seizure control device.

Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM

Epilepsy prediction through optimized multidimensional sample entropy and Bi-LSTM

An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

The Pinned-Photodiode (PPD) pixel design for indirect Time-of-Flight (ToF) systems has been optimized by optimum doping profile in the transfer tunnel and deep trench isolation in this paper. The pixel is elaborated based on the TCAD process. In simulate the proposed pixel design, its performance of demodulation contrasts have improved 26.09% at the working frequency of 40 MHz with 850 nm incident light. Also, the number of crosstalk electrons has been suppressed by 43.34% by giving 4 um trench isolation in the proposed pixel design.

A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF Application

Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware scheme is applied to the key modules, including PIE decoding and command receiving. And Galoi linear feedback shift register (LFSR) and double-edge-triggered techniques help to improve clock efficiency and reduce the impact of frequency variation in data link portions. Additionally, a novel custom ratioed logic style is adopted in key modules to fundamentally solve the speed problem at ultra-low-voltage. The proposed baseband processor was fabricated in 90nm CMOS as well as the regular design with the same function. In measurement the proposed design indicates good robustness and much more competent for subthreshold operation. It can operate below 0.3 V with power consumption below 130 nW.

Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells

Ultra low-power and high energy-efficient digital FIR filters and magnitude summation circuit are the key modules in spectral feature extraction (SFE) of portable thin-battery neural signal processing chips. A tailored SFE module design is presented in this brief. By adopting custom appropriate multiply-accumulate (MAC) circuits and novel ratioed logic style in custom standard cells’ design, the proposed SFE design is simplified with shorter logical path and faster subthreshold logic complex gates. Accuracy analysis is carried out to optimize the circuit structure with acceptable calculated results. Fabricated in 90 nm CMOS technology, the design has achieved 30% reduction of silicon area and 0.2 V lower supply voltage (hence over 50% elimination of power dissipation) in measurement, while compared to other regular works by standard design method. And the accuracy lost is within tolerant range.

A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors

Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware ideas are applied to the processor, including data link portions. Importantly, a novel custom ratioed logic style is adopted in key modules to fundamentally solve the speed problem at ultra-low-voltage. The proposed baseband processor was fabricated in 90nm CMOS as well as the regular design with the same function. In measurement the proposed design indicates good robustness and much more competent for subthreshold operation. It can operate at minimum 0.28V supply with power consumption of 129 nW.

Subthreshold passive RFID tag's baseband processor core design with custom modules and cells

An innovative logic style is proposed to achieve faster logic propagation in subthreshold operation: the Active Controlled Ratioed Logic (ACRL). It is an complete improvement and optimization from previous ratioed logic styles with pull-up current control and modified branches tailored to very-low supply voltage and ultra-low power. Even without proper control of its load current at the pre-drive stage, the active power of ACRL cells can be suppressed to a comparable magnitude of static CMOS logic cells leakage. General logic cells and complex circuit designs were fabricated in 90 nm CMOS technology. In measurement they are 30–70% faster than those of static and dynamic CMOS styles, and with lower power when the logic activity rises to a certain level.

Weiwei Shi

Papers

A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF Application

Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells

A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors

Subthreshold passive RFID tag's baseband processor core design with custom modules and cells

A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below