https://iopscience.iop.org/article/10.7567/JJAP.56.04CC05/pdf

Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus

In this paper, an efficient hybrid modeling method is presented for power integrity analysis of multilayer printed circuit boards (PCBs) and advanced electronic packages, with multiple power-ground planes, multiple vias, and external loads such as decoupling capacitors. Each parallel-plate pair, which consists of two consecutive conductor plates functioning as either power or ground in the PCBs or packages, is modeled as 2D generalized transmission line equations (GTLE). Equivalent circuits are used to model the vias and external loads. Numerical validation reveals that the hybrid modeling method produces accurate simulation results with much less central processing unit time and memory requirements than 3-D full-wave approaches.

Hybrid modeling method for power integrity simulation and analysis of multilayer electronic packages

A physics-based equivalent circuit model of on-chip decoupling capacitor for chip modelling is proposed for use in accurate power integrity (PI) analysis. The proposed model can be easily applied to on-chip decoupling capacitor design based on the construction flow. The accuracy of the model has been verified with circuit simulation. By using this model and an incomplete one, a case study of chip-package co-simulation in H-spice environment is investigated, which successfully demonstrate the purpose of the proposed model.

Wen-Wei Chen

Papers

A physics-based model of on-chip decoupling capacitor for accurate power integrity analysis