A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory. The primary and secondary memories are interconnected by a first multi-line bus for transferring a multi-bit word read from the secondary memory to the primary memory, and by a second multi-line bus for transferring a multi-bit word read from the primary memory to the secondary memory. The secondary memory is linked to a main memory by a second data output line and a second data input line for sequential transmission of bits to exchange multi-bit words during a writeback and refill operation. In a preferred embodiment, data inputs of the primary memory and the secondary memory are wired in parallel to a serial-parallel shift register that is used as a common write buffer.

Integrated circuit chip having primary and secondary random access memories for a hierarchical cache

A self-identifying scheme which permits a variety of integrated circuit semiconductor memory modules to inform a host processor as to each individual memory accessing speed or accessing time. Pre-encoded circuits within each memory module generate a coded signal when that module is selected by the host processor. The coded signal identifies the type of memory accessed, permitting the host processor to transfer information at a rate determined by the memory accessed.

Self identifying scheme for memory module including circuitry for identfying accessing speed

A microcomputer having an instruction memory is provided with a high-speed sense amplifier which can selectively operate in either of a high-speed operation mode or a low-speed operation mode. The high-speed sense amplifier is activated full time or at a large duty rate in the high-speed operation mode and is activated at a low-duty rate in the low-speed operation mode. By operating at a low-duty rate in the low-speed mode, a considerable power savings is realized while retaining the high speed benefits of the sense amplifier, which may be in the form of a current mirror-type sense amplifier or the like.

Microcomputer having high-speed and low-speed operation modes for reading a memory

An EPROM which includes on-chip circuitry for selecting alternate addressing. An EPROM cell, separate from the memory's array, is programmed to convert the memory to the alternate page mode addressing. The selection of the pages is done through the data lines. This frees address lines when the alternate mode is selected.

Apparatus for selecting alternate addressing mode and read-only memory

A control circuit, particularly for use in a phase-locked loop includes a read-only memory (ROM) having n address inputs divided into two groups, each group being addressed by first (A) and second (B) signals, and the memory device having words preprogrammed therein to provide an output having values (C) of a predetermined function of the first and second signals. In one embodiment the control circuit is employed in a phase-locked loop where one address group provides an analog version of the first signal to a voltage controlled oscillator, and application of the second signal to the second address group permits a step change in the output voltage to the VCO. In another embodiment, the first and second signals may comprise carrier signals and modulating signals in a phase-locked loop employed for frequency modulation.

Digital control of phase locked loops

A digital storage includes several sections having different time characteristics. Such sections are operated in the overlap mode and include a common address and control circuit. The fast sections store data which are accessed more frequently or which are addressed first when data blocks are transferred. The digital storage may be used in a storage hierarchy comprising a cache storage and wherein only data blocks positioned at main storage address boundaries are transferred to the cache storage.

Werner Dipl.-Ing. Strähle

Papers

Digital storage apparatus including sections exhibiting different access speeds