A bus guardian unit for a system in which processors, memories and other units are not grouped together physically but where any plurality of identical units e.g., three, can be made to operate in synchronism as though they were grouped together. Each unit would potentially be able to deliver data to any one of a number of buses and each of the three units operating in synchronism would normally deliver data to a different bus. Units accepting data from the bus system use data from three buses to determine the majority consensus of a triplet. The invention also allows idle units to be unpowered until needed either as replacements for failed units or else to provide extra computational capacity for system mission phases requiring same.

Synchronous fault tolerant multi-processor system

A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width Nc and a data field of Nf, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field Nf extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo Nc combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit Nc. A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.

Circuits for accessing a variable width data bus with a variable width data field

A multi-module, multi-port memory system includes modules having semiconductor memory circuits which require periodic refreshing to retain the contents stored therein. Priority circuits resolve conflicts between the multi-port access of the memory modules and the refreshing requirements of semiconductor memory circuits within the modules. The modules of the preferred embodiment are arranged in a polymorphous array of selectably expendable rows and columns. Modules utilizing different memory technologies may be combined within the address space of the array without interfering with independent multi-port access by various computer processors and other memory using devices.

Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system

A data field descriptor extends the flexibility of operand accesses by defining the attributes of a data field with regard to length, location and form of data representation at execution time. This delay of binding the operand accesses until execution time supports both data independence and security by permitting programs to be compiled without any restrictions imposed by the attributes of data fields. At execution time the necessary information is provided through a register so that the data field information may be correctly processed. With this feature a program is permitted to survive the change in formats of its input and output files without repeatedly undergoing the expensive operation of compilation. Also permitted is processing of files containing data field values which are not uniformly formatted throughout the file but which are self-defining through a data field descriptor.

Data processing system utilizing data field descriptors for processing data files

A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.

Communicating message request transaction types between agents in a computer system using multiple message groups

This disclosure relates to an information processing system employing plural processors which system is provided with a free field storage array to accommodate operands and data segments of any size and format. Each of the respective memory storage units is, in fact, structure oriented. However, pairs of such storage units are provided with isolation units having the capability of extracting and inserting fields of information independent of the memory structure. During a fetching operation, the isolation unit is adapted to fetch two contiguous parallel words and a shifting network or barrel switch is provided to position the desired field for transfer to the requesting device. During a store operation, the shifting network or barrel switch is employed to position incoming data into the proper bit location of the memory. The selected field is determined by the starting bit and the length field information provided by the memory control word and also by the type of operation requested. Each of the requesting devices is provided with its own interface unit that contains logic to construct a memory control word for each memory module involved in a fetch or store operation. In this manner, the entire array of memory units will appear to each of the requesting devices as being free field or without structure.

Information processing system having free field storage for nested processes

1336981 Digital computers BURROUGHS CORP 13 Nov 1970 [28 Nov 1969] 54201/70 Headings G4A and G4C The digital data processing system of copending Applications 54199/70 and 54200/70 is described with reference to its free field memory unit wherein operands and data segments can be of any size format. By this a requesting device, e.g. a central processor 10, an input/output module 18, or a memory extension controller 15, can extract or insert fields of data anywhere with the memory, a field being defined as a number of bits whose starting bit position may be anywhere within the memory. There may be up to sixteen memory modules 11 and sixteen requesting units, each memory unit being divided into a number of stacks, each stack having 8192 locations of 288 bits each. 256 bits are used for memory space and 32 bits for error coding making up four 72 bit words. Each memory module 11 has a field isolation unit 13 (Fig. 7, not shown) having a 144 bit fetch register which holds two 72 bit memory words, the first word being a copy of a memory word holding the present starting bit of a field and the second word being a copy of the memory word adjacent to the first word if the field is so long that it overflows from the first word. A requesting unit sends a memory control word to the unit 13, the word containing the absolute address of the starting bit of the field and the length of the field, and the address is used to access the two words. A shift register is used to position the words so that the starting position of the field is accessible, a buffer is provided together with parity checking for incoming and outgoing data, and an error register stores data on all other failures. Should the field length extend over more than two words then the next pair of adjacent words are accessed to accommodate the remaining field bits. Should a selected field overlap two memory storage units or modules then the requesting unit will have to generate a fresh memory control word. Provision for one bit error correction is mentioned, data transfer between the various units of Fig. 1, is in parallel and a priority circuit (Fig. 10, not shown) is provided to determine which requesting unit shall have access to one memory module.

White J

Papers

Information processing system having free field storage for nested processes

Digital electric information processing system