A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process conditions without considering process variations because of the lack of variational lithography models. A simple method to improve OPC results under process variations is to sample multiple process conditions across the process window, which requires long run times. We derive a variational lithography model (VLIM) that can simulate across the process window without much run-time overhead compared to the conventional lithography models. To match the model to experimental data, we demonstrate a VLIM calibration method. The calibrated model has accuracy comparable to nonvariational models, but has the advantage of taking process variations into consideration. We introduce the variational edge placement error (VEPE) metrics based on the model, a natural extension to the edge placement error (EPE) used in conventional OPC algorithms. A true process-variation aware OPC (PVOPC) framework is proposed used the VEPE metric. Due to the analytical nature of VLIM, our PVOPC is only about 2 to 3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. Thus our post-PVOPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.

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True process variation aware optical proximity correction with variational lithography modeling and model calibration

The present invention provides a system and method of modifying the mask layout shapes of an integrated circuit layout design to compensate for reticle field location-specific systematic CD variations resulting from mask writing process variations, lens imperfections in lithographic patterning, and photoresist process variations Called PLC (Process-optimized Layout Compensation), each set of compensation rules according to the present invention is specifically tailored for a particular mask-writer-patterning-tools-and-resist-process combination, and are performed on a reticle-wide basis Furthermore, for each geometric shape in the mask layout, the amount of modification is determined based on a categorization of the type of the shape, the specific location in the reticle field the particular shape falls in, its context (ie, surrounding patterns, orientation, etc), as well as certain photoresist parameters to be used in the patterning process

System and method for reducing patterning variability in integrated circuit manufacturing through mask layout corrections

Projection optical lithography

Computer-based design and verification tools provide integrated circuit layouts for use in chromeless phase lithography. A phase-mask design tool assigns feature size descriptors to circuit layout features, and mask features are configured using the feature size descriptors. Feature size descriptors can be assigned based on feature size ranges established based on a mask error function, feature dimensions with respect to a lithographic system resolution limit, or selected properties of aerial image intensity as a function of feature size. Circuit layout features are assigned mask features that include twin phase steps. In addition, circuit layout features associated with selected feature descriptors are assigned sub-resolution assist mask pattern portions or other mask pattern portions based on optical and process corrections.

Chromeless phase mask layout generation

Ability to predict process behavior under defocus has until now relied on explicit calculations, which while accurate, cannot be realistically used in full-chip optical and process correction strategies due to the long run times. In this work, we have applied a vector model for the optics, and a compact model for the resist development process. Simulations with these models are fast enough to be the basis of full-chip OPC. We verify this strategy with an independent set of measurements, and compare it to current lithographic process fitting strategies. The results indicate that by describing optical processes as accurately as possible, the model accuracy improves over a wider range of defocus conditions when compared to the traditional calibration method. As long as the calibration process successfully decouples optical and resist effects, relatively simple resist models deliver excellent accuracy within the noise level of the metrology measurements. Our data are based on one-dimensional and two-dimensional results using a 193nm system using 0.75 NA and off axis illumination with 6% attenuated phase shift mask. In all cases, a wide variety of sub-resolution assist feature rules were used in order to further test the ability of the models to predict various optical and resist environments.

Calibration of OPC models for multiple focus conditions

193nm lithography is very likely to be the pattern transfer method of choice for 65nm technology. This means lithography with a k1 factor in the range of 0.3, so strong resolution enhancement techniques (RET) are necessary. Until recently, alternating Phase Shift Masks (alt.PSM) seemed to be the only viable option. Rather stringent layout restrictions, complex mask manufacturing, and the throughput loss due to the required double exposure make this option rather costly. Double exposure of chromium masks or halftone (embedded) PSM with dipole illumination (DDL), or single exposure of chrome-less PSM (CPL) are evaluated as alternatives with proven resolution for the minimum feature size. Both techniques need sub-resolution features to compensate for their sub-optimum performance on either isolated lines or on lines of about twice the minimum width (in case of CPL). To linearize such highly non-linear pattern transfer processes, model-based Optical Proximity effect Correction (OPC) is mandatory for both options.
This paper demonstrates the automated generation of the basic mask writing data for both DDL and CPL for arbitrary layouts, followed by model-based OPC, using Calibre for both steps. Sufficient pattern fidelity and pattern robustness (over a 300nm defocus range) has been shown for a gate/polysilicon layer of a 65nm layout. The results were obtained using masks with reasonable mask specifications.

Alternatives to Alternating Phase Shift Masks for 65nm

Mask making yield is seriously affected by un-repairable mask defects. Up to now, there is only one size specification for critical defects, which has to be applied to any defect found. Since recently, some mask inspection tools offer the capability to inspect different features on one mask with different sensitivity. Boolean operations can be used to segregate mask features into more and less critical. In this paper we show the MEEF (Mask Error Enhancement Factor), which determines from the mask / wafer pattern transfer the actual effectiveness of mask errors, as an objective and relatively easily determinable parameter to assess the printability of mask defects. Performing OPC, a model-based OPC tool is aware of the MEEF, and can also provide the capability for the additional information handling, which is needed to supply the mask maker with a set of data layers of different defect printability for one mask layer.

MEEF-based mask inspection

In this paper, we will investigate methods for adapting model-based OPC tools to do layout correction (biasing) for mask makgin proximity effects. (Mask Proximity Correction). We will discuss three aspects of this problem: (1) typical models to use for mask making; (2) calibration of the model using mask measurement data; (3) one-pass versus two-pass flows for correction of mask making proximity effects.

Wilhelm Maurer

Papers

Chromeless phase mask layout generation

Calibration of OPC models for multiple focus conditions

Alternatives to Alternating Phase Shift Masks for 65nm

MEEF-based mask inspection

Flows for model-based layout correction of mask proximity effects