A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal. A transconductance amplifier compares the feedback signal to a reference voltage, and generates first and second currents corresponding thereto. These currents are converted to the first and second control signals by a control circuit, which includes a current mirror. The control circuit provides good immunity from power supply fluctuations.

Method and system for controlling the duty cycle of a clock signal

A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.

Programmable phase shift and duty cycle correction circuit and method

A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.

Test circuit, system, and method for testing one or more circuit components arranged upon a common printed circuit board

A wireless communication IC exchanges data with an external device by receiving a radio signal having a given carrier frequency as power supply from the external device through an antenna. The wireless communication IC includes a capacitor for storing electric power, a diode placed between one end of the antenna and the capacitor, for supplying a charge current of the radio signal to the capacitor on a half cycle of the received radio signal; and a load modulation circuit. The load modulation circuit is driven by receiving power supply from the capacitor on another half cycle of the radio signal different from a half cycle for supplying a charge current to the capacitor.

Wireless communication IC and wireless communication information storage medium using the same

A single-phase motor driving circuit includes a controller for outputting a control signal to drive a single-phase motor in a period in which a saw-tooth voltage of a predetermined cycle is larger than a duty setting voltage based on a result of comparing a detected temperature voltage changed based on a temperature detected by a temperature detecting device with a starting duty setting voltage increased with time while a voltage smaller than the detected temperature voltage at the time of starting the single-phase motor is set as an initial value. The controller sets the duty setting voltage as the starting duty setting voltage when the result of the comparison shows that the starting duty setting voltage is smaller than the detected temperature voltage, and the duty setting voltage as the detected temperature voltage when the starting duty setting voltage is larger than the detected temperature voltage.

Driving a single-phase motor

A controller that is linearly responsive to an input voltage provides continuously adjustable control of the width of a periodically repeating digital pulse, thereby achieving a linear voltage to duty-cycle ratio transfer function. The circuit of the present invention includes a master clock input, a ratio control voltage input, a controlled duty cycle clock output, a high gain amplifier configured as an integrator having differential inputs, each equipped with a low pass filter, a controlled current source, a resettable timing capacitor, a threshold detector and a reference pulse generator.

William H. Laletin

Papers

Controller for generating a periodic signal with an adjustable duty cycle