A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area In the exposure process, those transfer areas are overlaid one upon another in the same chip region

Manufacturing method of semiconductor integrated circuit device

A method and system conduct an auction for advertising across multiple markets. A first market conducts a first auction for a first advertising impression. A first bid is selected as the auction winner and a ratio is computed as the first bid plus a spread to the second highest bid. The price to be paid is the lower of the first bid or the first bid multiplied by the ratio. The first bid, second bid, and spread are transmitted to a second market for a second advertising impression auction. The second market respects the rules of the first market's auction where such that if the first bid is selected as the winner, a ratio is computed as the first bid plus the spread to the next highest bid. The price to be paid for the second impression is the first bid multiplied by the new ratio.

Managing bids in a real-time auction for advertisements

A method of printing a pattern having vertically oriented features and horizontally oriented features on a substrate utilizing dipole illumination, which includes the steps of: identifying background areas contained in the pattern; generating a vertical component mask comprising non-resolvable horizontally oriented features in the background areas; generating a horizontal component mask comprising non-resolvable vertically oriented features in the background areas; illuminating said vertical component mask utilizing an X-pole illumination; and illuminating said horizontal component mask utilizing a Y-pole illumination.

Orientation dependent shielding for use with dipole illumination techniques

The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.

Methods of Forming Patterns in Semiconductor Constructions, Methods of Forming Container Capacitors, and Methods of Forming Reticles Configured for Imprint Lithography

Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.

Method and apparatus for designing and integrated circuit

Photoresist on a wafer is exposed using tiles on a mask that improve flare performance Features that are not to be exposed on the photoresist correspond to features on the mask The various features are surrounded by other features that vary and thus affect flare differently Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist Thus the tiles reduce flare but do not alter the desired pattern in the photoresist

Non-resolving mask tiling method for flare reduction

A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer

A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. To determine the location of subresolution features the location of design and processing features is determined and the subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design and processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

William L. Wilkinson

Papers

Method and apparatus for designing and integrated circuit

Non-resolving mask tiling method for flare reduction

Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer

Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer and structure thereof