The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (DPL). However, there is very little study on TPL layout decomposition. In this paper, we show that TPL layout decomposition is a more difficult problem than that for DPL. We then propose a general integer linear programming formulation for TPL layout decomposition which can simultaneously minimize conflict and stitch numbers. Since ILP has very poor scalability, we propose three acceleration techniques without sacrificing solution quality: independent component computation, layout graph simplification, and bridge computation. For very dense layouts, even with these speedup techniques, ILP formulation may still be too slow. Therefore, we propose a novel vector programming formulation for TPL decomposition, and solve it through effective semidefinite programming (SDP) approximation. Experimental results show that the ILP with acceleration techniques can reduce 82% runtime compared to the baseline ILP. Using SDP based algorithm, the runtime can be further reduced by 42% with some tradeoff in the stitch number (reduced by 7%) and the conflict (9% more). However, for very dense layouts, SDP based algorithm can achieve 140× speed-up even compared with accelerated ILP.

/pdf/layout-decomposition-for-triple-patterning-lithography-1bak910stu.pdf

Layout decomposition for triple patterning lithography

In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area In the exposure process, those transfer areas are overlaid one upon another in the same chip region

Manufacturing method of semiconductor integrated circuit device

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

https://www.cerc.utexas.edu/utda/publications/C130.pdf

Implications of triple patterning for 14nm node design and patterning

As lithography continues to increase in difficulty with low k1 factors, and ever-tighter process margins, model-based optical proximity correction (OPC) is being used for the majority of patterning layers. As a result, the engineering effort consumed by the development and calibration of OPC models is continuing to increase at an alarming rate. One of the major focal points of this effort is the increasing emphasis on improving the accuracy of the model-based OPC corrections. One of the major contributors to final OPC accuracy is the quality of the resist model. As a result of these trends, the number of sample points used to calibrate OPC models is increasing rapidly from generation to generation. However, this increase is largely due to an antiquated approach to the construction of these calibration sets, focusing on structure variations. In this study, a new approach to the calibration of a resist model will be proposed based upon the location of calibration structures within the actual resist space over which the resist model is expected to be predictive.

Improving model-based OPC performance for the 65-nm node through calibration set optimization

Self-aligned double pattering (SADP) has been adapted as a promising solution for sub-30nm technology nodes
due to its lower overlay problem and better process tolerance. SADP is in production use for 1D dense patterns
with good pitch control such as NAND Flash memory applications, but it is still challenging to apply SADP to
2D random logic patterns. The favored type of SADP for complex logic interconnects is a two mask approach
using a core mask and a trim mask. In this paper, we first describe layout decomposition methods of spacer-type
double patterning lithography, then report a type of SADP compliant layouts, and finally report SADP
applications on Samsung 22nm SRAM layout. For SADP decomposition, we propose several SADP-aware layout
coloring algorithms and a method of generating lithography-friendly core mask patterns. Experimental results
on 22nm node designs show that our proposed layout decomposition for SADP effectively decomposes any given
layouts.

/pdf/layout-decomposition-of-self-aligned-double-patterning-for-5a3abapvxp.pdf

Layout decomposition of self-aligned double patterning for 2D random logic patterning

Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged.

Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20) The MOS metallic gate electrode layer (20) is covered with an ARC layer (22) The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28) The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed

Kevin Lucas

Papers

Implications of triple patterning for 14nm node design and patterning

Improving model-based OPC performance for the 65-nm node through calibration set optimization

Layout decomposition of self-aligned double patterning for 2D random logic patterning

Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process

Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation