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William R. Flederbach

Researcher at Qualcomm

Publications -  6
Citations -  48

William R. Flederbach is an academic researcher from Qualcomm. The author has contributed to research in topics: Integrated circuit & Die (integrated circuit). The author has an hindex of 3, co-authored 6 publications receiving 48 citations.

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Patent

Method and apparatus for a diffusion bridged cell library

TL;DR: In this article, the authors propose a library of continuous diffusion compatible (CDC) cells for designing an integrated circuit, which includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell.
Patent

Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems

TL;DR: In this paper, the adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuits after a voltage droop occurs in a power supply supplying power to the clock circuit.
Patent

A bi-modal power delivery scheme for integrated circuits that enables fine grain power management for multiple functional blocks on a single die

TL;DR: In this article, a bi-modal and fine grained power delivery to an integrated circuit (200) comprising functional blocks (202 1...202 M ) is described. But the performance of the functional block is limited by the duty cycle of the first and second power sources.
Patent

Method and apparatus for updating replacement policy information for a fully associative buffer cache

TL;DR: In this paper, techniques and apparatus are provided for updating replacement policy information for a fully associative buffer cache. And a method is provided to evict entries from the second cache memory based on the updated policy information.
Patent

Bi-modal power delivery scheme for an integrated circuit comprising multiple functional blocks on a single die to achieve desired average throughput for the integrated circuit

TL;DR: In this paper, a first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block and a second power source can be derived from the first source using on-die regulators or provided independently.