From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets. The objective of the layer assignment problem in general is to minimize the number of vias required. Thus, it is also referred to as the via minimization problem. In a via minimization problem, if the topology of the given layout is fixed, the problem is referred to as a constrained via minimization (CVM) problem. On the other hand, if both the topology of the layout and the layer assignment are to be decided, it is referred to as an unconstrained via minimization (UVM) problem. In this paper, both the CVM and UVM problems are studied. For the CVM problems, efficient algorithms which can be easily modified to take extra constraints into consideration are proposed. Experimental results show that the proposed algorithms for the CVM problem are time efficient compared with existing algorithms and generate better (near-optimal) results. For the UVM problems, a new heuristic approach is presented which generates better results but takes longer computing time. In the CVM problem, some vias are "essential" to the given layout. That is, they have to be selected and cannot be replaced by other possible vias. An efficient algorithm for identifying essential vias is also presented and discussed in this paper.

Efficient Algorithms for Layer Assignment Problem

An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm. This technique is dependent solely upon the interconnect topology and the direction of signal flows between cells and nets. The formulation of cell gains is extended to model the effect of cell replication, and the necessary modifications to the algorithm are described. >

A cell-replicating approach to minicut-based circuit partitioning

The authors study the channel pin assignment (CPA) problem subject to position constraints, order constraints, and separation constraints. The problem is to assign two sets of terminals to the top and the bottom of a channel to minimize channel density. It is shown that the problem is NP-hard in general and polynomial time-optimal algorithms are presented for a case where the relative orderings of the terminals on the top and the bottom of the channel are completely fixed. The problem of channel routing with movable modules is introduced, and it is shown that it is a special case of the CPA problem under the formulation, and can be solved optimally in polynomial time. How the algorithms can be incorporated into standard-cell and building-block layout systems is discussed. Experimental results indicate that substantial reduction in channel density can be obtained by allowing movable terminals. >

Optimal channel pin assignment

An optimal algorithm for the maximum alignment of terminals

In this paper we consider the problem of local wiring in a VLSI chip. The problem is one of interconnecting two sets of terminals, one set on each side of a wiring channel, in accordance with a given interconnection pattern, and to accomplish this while minimizing some objective function. We make the further assumption that the terminals are not rigidly positioned and can be "moved" provided that this does not change the structural intent of the circuit. Several objective functions are considered-channel width, channel length, channel area, channel perimeter, number of via holes, as well as some constrained objective functions. For some of these objective functions, we are able to find polynomial time optimal algorithms while, for others, we prove NP-completeness and suggest efficient heuristics.

Wong

Papers

Optimal Wiring of Movable Terminals