A multiplier architecture (Fig. 5) in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure (Figs. 3, 12 or 13) in order to achieve a small floor plan (Fig. 4) when reduced to silicon. A Hekstra-type multiplier is modified by replacing many of the full adders circuits (F) with compressor circuits (C; Figs. 8-11) in a manner that preserves the balance of the signal delays between the various propagation paths through the summing stages (SA, MS). The result is an architecture having a regular layout that greatly facilitates its implementation in silicon.

Fast regular multiplier architecture

The improved electrooptic signal processing relies upon matrix-matrix multiplication using twos complement arithmetic. A source of pulse collimated light illuminates two two-dimension spatial light modulators that operate in a reflective mode through a polarizing beamsplitter. Each of the spatial light modulators has a matrix of optically encoded information of numbers in the twos complement binary representation so that a mixed binary representation of signals is generated within the two-dimensioned photodetector array. The mixed binary representation signals are decoded to a twos complement binary representation or a decimal representation to be useful for more conventional processing techniques. The twos complement arithmetic when incorporated with the electrooptic architecture provides for a convenient means for handling bipolar numbers, avoids the need for matrix partitioning when the matrices are real and offers a means to improve accuracy over conventional optical analog techniques.

Electrooptical matrix multiplication using the twos complement arithmetic for improved accuracy

A method and apparatus that combines the same basic hardware elements in several ways to perform a plurality of arithmetic operations over different numbers of operands of different lengths. The allowed options include the multiplication and summing of several operands in a single operation. The reuse of hardware elements is obtained by the use of a multiplication hardware structure together with multiplexer logic (or similar selection logic) at appropriate points in the hardware structure, which allows a minimum of extra hardware and a small number of extra gate delays along any critical path, thereby ensuring that the flexibility to use different operand lengths and numbers of operands incurs only a small penalty in processing speed and/or chip area in a VLSI circuit implementation.

Reconfigurable arithmetic datapath

A multi-bit overlapped scanning multiplication system using overlapped partial products in a matrix, accepts and multiplies either sign-magnitude operands or signed binary operands without correction, conversion, or complementation of operands or results.

Two's complement multiplication with a sign magnitude multiplier

The invention performs the multiplication and/or accumulation of digital numbers in either two's complement of unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.

Digital multiplier architecture with triple array summation of partial products

Apparatus and methods for performing the parallel m-bit by n-bit multiplication of two binary 2's complement numbers by converting the multiplication process to an equivalent parallel array addition in which the operands are positive partial products including (1) terms formed by ANDing a multiplier bit (or its complement), and (2) a multiplicand bit (or its complement) and five additional partial product terms. The resulting simplifications permit circuit realization in the form of an array of 3-bit adders each formed from a combination of threshold logic modules.

Wooley Bruce Allen

Papers

Two{3 s complement parallel array multiplier