This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14× by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 ? J per feature vector.

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A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System

This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14x by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 μJ per feature vector.

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

This work introduces the use of compressed sensing (CS) algorithms for data compression in wireless sensors to address the energy and telemetry bandwidth constraints common to wireless sensor nodes. Circuit models of both analog and digital implementations of the CS system are presented that enable analysis of the power/performance costs associated with the design space for any potential CS application, including analog-to-information converters (AIC). Results of the analysis show that a digital implementation is significantly more energy-efficient for the wireless sensor space where signals require high gain and medium to high resolutions. The resulting circuit architecture is implemented in a 90 nm CMOS process. Measured power results correlate well with the circuit models, and the test system demonstrates continuous, on-the-fly data processing, resulting in more than an order of magnitude compression for electroencephalography (EEG) signals while consuming only 1.9 μW at 0.6 V for sub-20 kS/s sampling rates. The design and measurement of the proposed architecture is presented in the context of medical sensors, however the tools and insights are generally applicable to any sparse data acquisition.

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Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ?W. The measured input-referred noise is 6.08 ? Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ?W. The design is implemented in 0.35-?m complementary metal-oxide semiconductor technology with the channel pitch of 200 ?m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg2+/high-K+ epileptic seizure model in an intact hippocampus of a mouse.

/pdf/the-128-channel-fully-differential-digital-integrated-neural-2de1s1iso7.pdf

The 128-Channel Fully Differential Digital Integrated Neural Recording and Stimulation Interface

Algorithmically and energetically efficient computational architectures that operate in real time are essential for clinically useful neural prosthetic devices. Such devices decode raw neural data to obtain direct control signals for external devices. They can also perform data compression and vastly reduce the bandwidth and consequently power expended in wireless transmission of raw data from implantable brain-machine interfaces. We describe a biomimetic algorithm and micropower analog circuit architecture for decoding neural cell ensemble signals. The decoding algorithm implements a continuous-time artificial neural network, using a bank of adaptive linear filters with kernels that emulate synaptic dynamics. The filters transform neural signal inputs into control-parameter outputs, and can be tuned automatically in an on-line learning process. We provide experimental validation of our system using neural data from thalamic head-direction cells in an awake behaving rat.

/pdf/a-biomimetic-adaptive-algorithm-and-low-power-architecture-pvk5atsi5q.pdf

A biomimetic adaptive algorithm and low-power architecture for implantable neural decoders

An ultra-low-power circuit for wireless neural recording and stimulation is provided. The circuit includes a neural amplifier with adaptive power biasing for use in multi-electrode arrays and a decoding and/or learning architecture. An impedance-modulation telemetry system provides low-power data telemetry. Also, the circuit includes a wireless link for efficient power transfer, and at least one circuit for wireless stimulation of neurons.

Low-power analog architecture for brain-machine interfaces

Summary

Frequency compensation of a multistage operational amplifier (op-amp) is normally performed through solving nodal equations of an equivalent circuit to obtain the op-amp's final transfer function. The process is often very tedious and offers little insight into the roles of the selected compensation scheme. In this paper, we present a graphical design approach for two-stage and three-stage op-amps with active feedback Miller compensation. By viewing frequency compensation as a standard feedback problem, we can utilize the well-known graphical tools such as the root locus and Bode plot to understand the effects of the compensation and to estimate the locations of the closed-loop poles and zeros of the op-amp. Intuitive graphical design procedures for two-stage and three-stage op-amps are also formulated. To show its effectiveness, we illustrate our design approach through the design of a three-stage op-amp in a standard 0.18-μm complementary metal-oxide-semiconductor (CMOS) process. With a load capacitance of 500 pF, post-layout simulations show that the op-amp achieves a low-frequency gain of 144 dB, a phase margin of 58∘, and a unity-gain frequency of 1.38 MHz while consuming a total bias current of 31 μA from a 1.8-V supply voltage. Comparisons with the published amplifiers show that our op-amp achieves the figure of merits comparable to those of the state of the art. Copyright © 2015 John Wiley & Sons, Ltd.

Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation

This brief presents a frequency compensation technique to improve the settling time in driving moderate capacitive load (10–20 pF) of a low-power ( $ {\mu }{\mathrm{ W}}$ ) class-AB super buffer, wherein previously reported super buffers exhibit poor stability performance. From post-layout simulations in a 0.18- $ {\mu }\text{m}$ CMOS process, the proposed super buffer—while driving a 10-pF load and consuming less than 1 ${\mu }\text{A}$ of quiescent current from a 1.2-V supply voltage—achieves a factor of 1.8 (positive output direction) and 5.1 (negative output direction) reduction in the settling time compared to before compensation. We also validated the proposed technique through the measurements of a super buffer built on a protoboard with commercial discrete MOS transistors.

A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement

A micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays is provided. The micropower neural amplifier includes a low noise gain stage. The low noise gain stage is implemented using an amplifier and pseudoresistor elements.

Woradorn Wattanapanitch

Papers

A biomimetic adaptive algorithm and low-power architecture for implantable neural decoders

Low-power analog architecture for brain-machine interfaces

Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation

A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement

Micropower neural amplifier with adaptive input-referred noise