This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Silicon-Germanium (SiGe) technology effectively merges the desirable attributes of conventional silicon-based CMOS manufacturing (high integration levels, at high yield and low cost) with the extreme levels of transistor performance attainable in classical III-V heterojunction bipolar transistors (HBTs). SiGe technology joins together on-die high-speed bandgap-engineered SiGe HBTs with conventional Si CMOS to form SiGe BiCMOS technology, including all the requisite RF passive elements and multi-level thick-Al metalization required for high-speed circuit design. Such an silicon-based integrated circuit technology platform presents designers with an ideal division of labor for realizing optimal solutions to many performance-constrained mixed-signal (analog + digital + RF) systems. The unique bandgap-engineered features of SiGe HBTs enable several key merits with respect to operation across a wide variety of so-called “extreme environments”, potentially with little or no process modification, ultimately providing compelling advantages at the circuit and system level, across a wide class of envisioned commercial and defense applications. Here we give an overview of this interesting field, focusing primarily on the intersection of SiGe HBTs, and circuits built from them, with radiation-intense environments such as space.

Radiation Effects in SiGe Technology

This paper presents a 35-GS/s, 4-bit flash ADC-DAC with active data and clock distribution trees. At mm-wave clock frequencies, skew due to mismatch in the clock and data distribution paths is a significant challenge for both flash and time-interleaved converter architectures. A full-rate front-end track and hold amplifier (THA) may be used to reduce the effect of skew. However, it is found that the THA output must then be distributed to the comparators with a bandwidth greater than the sampling frequency in order to preserve the flat regions of the track and hold waveform. Instead, if the data and clock distribution have very low skew, the THA can be omitted thus obviating the associated nonlinearities and resulting in improved performance. In this work, a tree of fully symmetric and linear BiCMOS buffers, called a ldquodata treerdquo, distributes the input to the comparator bank with a measured 3-dB bandwidth of 16 GHz. The data tree is integrated into a complete 4-bit ADC including a full-rate input THA that can be disabled and a 4-bit thermometer-code DAC for testing purposes. The chip occupies 2.5 mm times 3.2 mm including pads and is implemented in 0.18 mum SiGe BiCMOS technology. The ADC consumes 4.5 W from a 3.3 V supply while the DAC operates from a 5 V supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3-dB effective resolution bandwidth of 8 GHz and a full-scale differential input range of 0.24 Vpp. With the THA enabled, the performance degrades rapidly beyond 8 GHz to less than 1-bit, but with the THA disabled, the ENOB remains better than 3-bits for inputs up to 11 GHz with an SFDR of better than 26 dB.

/pdf/a-35-gs-s-4-bit-flash-adc-with-active-data-and-clock-3b649szlrb.pdf

A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees

This paper presents a 40-GS/s continuous-time bandpass DeltaSigma analog-to-digital converter centered at 2 GHz for wireless base station applications. The ADC consists of a fourth-order loop with multiple feedback and is designed entirely in the s-domain. The circuit achieves an SNDR of 55 dB and 52 dB over bandwidths of 60 MHz and 120 MHz, respectively, and an SFDR of 61dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8 to 2 GHz. It employs a Gm-LCVAR filter based on a MOS-HBT cascode transconductor with an NFMIN of 2.29 dB. The entire circuit is implemented in a 130-nm SiGe BiCMOS technology with 150-GHz fT SiGe HBT and dissipates 1.6 W from a 2.5-V supply

A Low-Noise 40-GS/s Continuous-Time Bandpass $\Delta\Sigma$ ADC Centered at 2 GHz for Direct Sampling Receivers

A 30-GS/sec CMOS track and hold amplifier (THA) is designed and fabricated in a 0.13-μm technology. The chip operates from a 1.8-V supply and consumes 270 mW. The THA employs a low noise TIA input stage and a switched source follower (SSF) track and hold block. The SSF topology overcomes the shortcomings of switched series transistors by eliminating the use of a series switch all together. The measured single-ended S-parameters show an input and output return loss of better than -10 dB up to 35 GHz and 7 GHz of bandwidth when the circuit is operated in track mode. The measured total harmonic distortion of the THA is better than -29 dB.

A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology

We present the design and implementation of an ultra-high-speed SiGe BiCMOS track-and-hold amplifier (THA) for use in high-speed analog-to-digital converters. The use of a degeneration inductor in the input buffer significantly improves the performance of the THA. The THA was fabricated in a commercially-available 0.25 /spl mu/m 200 GHz SiGe HBT BiCMOS process technology. The circuit occupies an area of 1.2 mm/sup 2/, and exhibits -49.5 dBc of total harmonic distortion (THD) when operated at a sampling frequency of 12.5 GHz with an input frequency of 3.0 GHz. Operating from a 3.5 V supply, the total power consumption is 0.7 W. To our knowledge, this circuit is the fastest 8-bit Si-based THA achieved to date.

An 8-bit, 12 GSample/sec SiGe track-and-hold amplifier

A low-power, X-band low-noise amplifier (LNA) is presented. Implemented with 180 GHz silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs), the circuit occupies 780times660 mum2. The LNA exhibits a gain of 11.0 dB at 9.5 GHz, a mean noise figure of 2.78 dB across X-band, and an input third-order intercept point of -9.1 dBm near 9.5 GHz, while dissipating only 2.5 mW. The low-power performance of this LNA, together with its natural total-dose radiation immunity, demonstrates the potential of SiGe HBT technology for near-space radar applications

A Low-Power, $X$ -Band SiGe HBT Low-Noise Amplifier for Near-Space Radar Applications

An ultra-high-speed track-and-hold amplifier (THA) using a switched-emitter-follower (SEF) configuration is presented. Implemented in a commercially-available 0.18 /spl mu/m 120 GHz SiGe HBT BiCMOS technology, the THA core occupies a compact area of only 120 /spl times/ 200 /spl mu/m/sup 2/. The THA can operate at a sampling rate of 18 GS/sec with a total harmonic distortion (THD) of -32.3 dBc, and dissipates 128 mW, significantly smaller than other THAs in the literature operating at similar sampling rates.

http://ieeexplore.ieee.org/iel5/10254/32673/01531774.pdf

A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier

An ultra-high-speed SiGe track-and-hold amplifier (THA) using a switched-emitter-follower (SEF) configuration is presented. Operating off a +5.5 V power supply, this THA exhibits -32.4 dBc of total harmonic distortion (THD) when sampling a 10 GHz input signal at the rate of 40 GS/s, and reaches -50.5 dBc of THD when sampling a 2 GHz input at 12 GS/s. Compared to the THAs published in the literature with an operational range from 10 GS/s to 20 GS/s, the present THA demonstrates a THD comparable to the best one achieved to date to our knowledge for Si technology, with much improved high-frequency characteristics. On the other hand, in the operational range of 30 GS/s and above, the present SiGe THA still exhibits robust characteristics compared to the fastest THAs in terms of linearity, power consumption, and sampling rate.

A 40 GS/s SiGe track-and-hold amplifier

This paper presents a low-power high-speed BiCMOS track-and-hold amplifier (THA). It combines the differential switched-emitter follower of (Vorenkamp and Verdaasdonk, 1992) with the low-droop output buffer presented in (Fiocchi et al., 2000). A test implementation consumes 70 mW of total power (30 mW THA). It works up to 15 GS/s, using minimum-size HBTs in a 0.25/spl mu/m 200 GHz SiGe BiCMOS technology. At 10 GS/s and an input signal of 1 GHz, the achieved THD corresponds to 6.8 bits accuracy. To our knowledge, the present circuit is by far the fastest THA with low power consumption and high accuracy.

Xiangtao Li

Papers

An 8-bit, 12 GSample/sec SiGe track-and-hold amplifier

A Low-Power, $X$ -Band SiGe HBT Low-Noise Amplifier for Near-Space Radar Applications

A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier

A 40 GS/s SiGe track-and-hold amplifier

A low-power, 10GS/s track-and-hold amplifier in SiGe BiCMOS technology