The invention discloses a transaction processing method and device, computer equipment and a storage medium, and belongs to the technical field of databases. According to the invention, consistency detection is carried out on the read-write set of the target transaction; data exception formed by a single transaction can be accurately identified in a transaction submission stage; when consistency detection is passed, sets of transactions to be merged are obtained, the target transaction is combined with the historical transaction; under the condition that data exception does not exist after affairs are merged, a target transaction is committed. Data exception jointly formed by multiple transactions can be detected in a transaction merging mode; therefore, various data anomalies in the database system can be comprehensively identified; the transaction processing mechanism does not depend on a blocking technology or a dependency graph technology, the concurrency degree of the database system is prevented from being limited, it is not needed to traverse concurrent transactions to identify the existence of the dependency graph in the dependency graph, and the transaction processing efficiency of the database system is improved.

Transaction processing method and device, computer equipment and storage medium

The disclosure invention provides a method for executing a program compiled for a source architecture on a machine having a different target architecture, a non-transitory computer readable medium configured to store instructions for performing such a method, and a system for performing such a method

Load module compiler

Dynamic binary instrumentation is a code insertion technique for debugging a program without scattering its execution flow, while the program is running. Most dynamic instrumentations are implemented using dynamic binary translation techniques. Existing studies translated program codes dynamically by parsing the machine code stream to intermediate representation (IR) and then applying compilation techniques for IRs. However, they have high overhead during translation, which is a major cause of difficulty in applying the dynamic binary translation technique to the program which requires high responsiveness. In this paper, we introduce a light-weight dynamic binary instrumentation framework based on a novel dynamic binary translation technique which has low overhead while translating the program code. In order to reduce the translation overhead, our approach adopts a tabular-based address translation and exploits a translation bypassing scheme, which stores the translated address of a frequently called library function in advance. It then accesses the translated address and executes function codes without code translation when calling the function. Our experiment results demonstrated that the proposed approach outperforms the prior dynamic binary translation techniques from 2% up to 65%.

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Design and Implementation of a Dynamic Instrumentation Framework based on Light-weight Dynamic Binary Translation

A major challenge of Dynamic Binary Translation (DBT) is to efficiently handle the indirect branch. Conventionally, to translate indirect branches (IBs), DBT systems need to conduct address mapping between Source Binary Blocks (SBB) and Translated Binary Blocks (TBB). However, even a dedicated address mapping process still results in non-trivial performance overheads to DBT. This paper first provides exhaustive analysis of the overheads of address mapping, and finds that hash lookup, context switching and consistency maintenance are three main sources of overheads. To address these overheads, we further propose a novel approach called Virtual Branch Instruction Write-back (VBIW). The key idea is to dynamically write a Virtual Branch Instruction (VBI) into the SBB once the mapping is determined. Since the VBI contains the target TBB address of a branch, the costly address mapping can be eliminated for further reference of the same branch. In addition to theoretical analysis of VBIW, we also implement VBIW on a X86 to MIPS DBT system of Godson-3. The experimental results show that VBIW can reduce DBT execution time by 29.5% on average (ranging from 1.8% to 58.5%) for single threaded benchmarks, and by 19.6% on average (4.5% to 62.5%) for multithreaded benchmarks.

VBIW: Optimizing Indirect Branch in Dynamic Binary Translation

The embodiment of the invention provides a conflict detection method for a transactional memory, a transactional memory system and a microprocessor. The method comprises the following steps: during execution of an access operation of a first transaction, recording a read operation of the first transaction in a read set of the first transaction, and recording a write operation of the first transaction in a write set of the first transaction; and after finishing the execution of the first transaction, judging that a conflict exists between the first transaction and a second transaction if intersection sets between the write set of the first transaction and a read set of the second transaction are detected, wherein an execution ending time of the first transaction is ahead of an execution ending time of the second transaction. Through adoption of the conflict detection method for the transactional memory, the transactional memory system and the microprocessor provided by the embodiment of the invention, a relationship between a read set of a transaction ending firstly and a write set of a transaction ending secondly does not need to be compared, so that the problem of transactional conflicts caused by read-write association among the transactions is solved; the probability of the occurrence of conflicts among the transactions is lowered; and the performance of the transactional memory system is enhanced.

Conflict detection method for transactional memory, transactional memory system and microprocessor

This paper proposes a novel method to optimizing H.264 decoding on multi-core processors by exploiting color component level parallelism. Compared with sequential decoding and macro-block level parallelism, the proposed method achieves optimal balance between performance and scalability. The optimization scheme is mapped on a 64-bit MIPS multi-core processor, and is evaluated with standard test streams. Experimental results show that the method improves video decoding performance by 2 times on average without increasing memory consumption, and could be easily applied on other multi-core processors.

Xiaofu Meng

Papers

VBIW: Optimizing Indirect Branch in Dynamic Binary Translation

Conflict detection method for transactional memory, transactional memory system and microprocessor

Luminance and Chrominance Parallelization of H.264/AVC Decoding on a Multi-core Processor